Clock Delay Compensation for Power Supply Noise Jitter
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Solution Overview
Problem
Power supply noise (PSN) induces jitter in clock signals within integrated circuit devices, affecting data transmission between memory and controller devices, leading to adverse effects on data capture and transmission accuracy.
Innovation Solution
The system transmits power supply noise information to adjust the clock signal delay, generating compensating power supply induced jitter (PSIJ) that matches the jitter in the receiving clock signal, thereby reducing relative jitter and allowing higher frequency clocking without increasing bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signals are transmitted at higher frequencies to improve data transmission rate, then productivity increases, but power supply noise induces more jitter which worsens reliability
Solution Approach 1:
The patent transmits power supply noise information from the memory device to the controller device, where it is used to generate compensating jitter in the controller's clock signal. This converts the harmful PSN that causes jitter into a beneficial compensation mechanism, where the controller intentionally introduces matching jitter to cancel out the relative jitter between transmit and receive clock signals, thereby maintaining reliable data capture at higher transmission rates
Solution Approach 2:
The system implements a feedback loop where power supply noise information is transmitted from the memory device back to the controller device. This feedback allows the controller to adjust its clock signal characteristics based on the actual noise conditions experienced by the memory device, enabling dynamic compensation that maintains synchronization and reliability even at higher data transmission rates
2Productivity
If clock frequency is increased to improve data rate, then productivity increases, but relative jitter between clock signals worsens leading to higher bit error rates
Solution Approach 1:
The patent transforms the harmful relative jitter caused by power supply noise into a beneficial compensation mechanism. By transmitting PSN information and generating matching jitter in the controller's clock signal, the system converts the timing precision degradation into an advantage where the jitter becomes common-mode between transmit and receive clocks, thereby maintaining effective timing precision at higher data rates
3Reliability
If power supply noise compensation is implemented to reduce jitter, then reliability improves, but device complexity increases due to additional noise information transmission and processing circuits
Solution Approach 1:
The patent implements multi-functionality by using existing communication infrastructure for noise information transmission. The power supply noise information is transmitted utilizing existing signal paths and protocols between memory and controller devices, rather than requiring dedicated noise communication channels. This allows the compensation mechanism to enhance reliability while minimizing additional circuit complexity by repurposing existing system resources
Solution Approach 2:
The system employs self-service by having each device generate and process its own compensating jitter based on transmitted noise information. The memory device transmits its experienced PSN characteristics, and the controller device autonomously generates the corresponding compensation jitter without requiring external intervention or complex coordinated control, thereby improving reliability through a relatively simple self-managing mechanism
Data Source
AI summary
A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.