Clock Delay Circuit for Phase And Duty Cycle Error Correction
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Solution Overview
Problem
Existing semiconductor circuits using multi-phase clock signals face challenges in correcting both phase errors and duty cycle errors, where phase error correction can introduce duty cycle errors and vice versa, leading to instability in clock signal operations.
Innovation Solution
A delay circuit and clock error correction device that include a first signal generator, inverting circuits, and a code control circuit to adjust delay times for clock signal edges based on delay and duty codes, allowing for simultaneous correction of phase and duty cycle errors by comparing and adjusting the phases and edges of multiple clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase error corrector is used to correct phase error, then phase error is corrected, but duty cycle error is introduced
Solution Approach 1:
The delay circuit is designed to perform both phase error correction and duty cycle correction functions simultaneously. By controlling different groups of delay units with separate control signals (first control signal for phase, second control signal for duty cycle), the circuit achieves multi-functionality, allowing it to correct both types of errors without requiring separate dedicated circuits for each function.
Solution Approach 2:
The delay circuit is divided into multiple delay units (first delay units and second delay units) that can be independently controlled. The first delay units are responsible for phase error correction while the second delay units handle duty cycle correction. This segmentation allows independent optimization and control of each correction function, preventing the interference that occurs in unified correction circuits.
2Manufacturing precision
If a duty cycle corrector is used to correct duty cycle error, then duty cycle error is corrected, but phase error is introduced
Solution Approach 1:
The delay circuit integrates both phase error correction and duty cycle correction capabilities in a single unified structure. By using separate control signals to independently manage different delay units, the circuit can perform duty cycle correction while maintaining phase accuracy, thus achieving multi-functionality without the trade-offs of separate dedicated circuits.
Solution Approach 2:
The delay circuit is segmented into first delay units controlled by a first control signal for phase error correction, and second delay units controlled by a second control signal for duty cycle correction. This segmentation enables independent control of each function, allowing duty cycle correction to be performed without introducing phase errors, as each segment operates independently based on its specific control signal.
3Reliability
If separate phase error corrector and duty cycle corrector are used, then both errors can be corrected individually, but system complexity increases and errors may interfere with each other
Solution Approach 1:
The patent merges the phase error correction and duty cycle correction functions into a single integrated delay circuit. By combining multiple delay units with independent control mechanisms within one circuit structure, the system achieves the error correction capabilities of separate correctors while reducing overall system complexity and eliminating the interference problems that arise from having multiple independent correction circuits.
Solution Approach 2:
The integrated delay circuit is designed with universal functionality to handle both phase error correction and duty cycle correction. By incorporating multiple controllable delay units that can be selectively activated based on the type of error present, the circuit provides a unified solution that reduces system complexity while maintaining comprehensive error correction capability.
Data Source
AI summary
A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals. The second inverting circuit is configured to adjust a second delay time for the first edge, the second edge, or both of the first edge and the second edge of the clock signal.