Clock Delay Control Circuit for Jitter-Resistant Phase Locking
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Solution Overview
Problem
Conventional delay-locked loops in semiconductor apparatuses face issues with precise phase detection due to jitter and power noise, leading to stuck phenomena where the delay value of the delay line cannot be updated, affecting synchronization with external clocks.
Innovation Solution
A clock generation circuit is designed with a delay line, delay modeling unit, phase detection unit, filter unit, and delay line control unit, where the filter unit generates update signals based on phase detection signals and a timer update signal to prevent stuck phenomena by forcibly updating the delay value when necessary, ensuring precise delay locking operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase detection is performed using conventional delay-locked loop, then phase difference compensation is achieved, but stuck phenomenon occurs when jitter or power noise prevents precise phase detection
Solution Approach 1:
The patent applies preliminary action by counting phase detection signals in advance before making a delay value update decision. The filter unit accumulates a predetermined number of phase detection signals and compares their levels to determine whether to generate an update signal, preventing stuck phenomena caused by transient jitter or noise that would otherwise cause erroneous single-signal updates.
Solution Approach 2:
The patent implements feedback by using the phase detection signal to control the delay line, which in turn affects the feedback clock phase. The filter unit continuously monitors phase detection signals and adjusts the delay value based on the accumulated comparison results, creating a closed-loop feedback system that maintains stable phase synchronization despite jitter or power noise interference.
2Speed
If delay value is updated based on single phase detection signal, then response speed is fast, but stuck phenomenon occurs due to jitter or power noise
Solution Approach 1:
The filter unit performs preliminary counting and comparison of a predetermined number of phase detection signals before generating an update signal. This preliminary processing ensures that the delay value is only updated when there is consistent phase difference evidence, preventing stuck phenomena while maintaining relatively fast response through the predetermined count threshold mechanism.
Solution Approach 2:
The patent uses partial action by counting only a predetermined number of phase detection signals rather than continuously updating based on every signal. This partial sampling approach filters out transient noise while maintaining adequate response speed, as the predetermined count threshold is set to balance between responsiveness and noise rejection.
3Speed
If filter unit generates update signal frequently, then phase synchronization is achieved quickly, but power noise causes erroneous updates
Solution Approach 1:
The filter unit counts a predetermined number of phase detection signals and compares their levels before generating an update signal. This preliminary accumulation process ensures that only consistent phase differences trigger updates, filtering out erroneous updates caused by power noise while maintaining adequate synchronization speed through the predetermined count threshold.
Solution Approach 2:
The filter unit acts as an intermediary between the phase detection unit and the delay line control unit. It processes the raw phase detection signals through counting and comparison operations, mediating between the fast but noisy phase detection and the delay value update mechanism, thereby filtering out erroneous updates while maintaining synchronization speed.
Data Source
AI summary
A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.