Fuse-Controlled Clock Delay for PVT-Stable Memory Output Timing
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Solution Overview
Problem
Conventional clock signal generating circuits in high-speed semiconductor memory devices, such as DDR SDRAM, are susceptible to Process, Voltage, and Temperature (PVT) fluctuations, leading to inconsistent data output timing due to variations in MOS transistor operating characteristics.
Innovation Solution
A clock signal generating circuit that utilizes a fuse unit to generate control signals for delaying the external clock signal, allowing for precise control of rising and falling clock signals through fuse cutting, ensuring synchronized data output despite PVT fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional clock signal generating circuits are used in high-speed semiconductor memory devices, then data processing speed can be increased through DDR SDRAM operation, but data output timing becomes inconsistent due to PVT fluctuations affecting MOS transistor operating characteristics
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the pulse width of internal clock signals through fuse cutting before the device operates. The fuse unit is configured to selectively cut fuses based on PVT conditions, thereby pre-determining the delay time of the delay unit and stabilizing the pulse width of internal clock signals before any data processing occurs. This prevents timing inconsistencies from developing during operation.
Solution Approach 2:
The patent changes the parameter of pulse width of internal clock signals based on PVT conditions. The fuse unit generates different control signals (first through fourth control signals) that adjust the delay time of the delay unit, thereby changing the pulse width parameters of rising and falling internal clock signals. This allows the system to adapt to PVT fluctuations by selecting appropriate parameter settings through fuse cutting.
2Device complexity
If the pulse width of internal clock signals is fixed, then circuit design is simplified, but the circuit cannot adapt to PVT fluctuations causing timing errors
Solution Approach 1:
The patent introduces dynamics by making the pulse width of internal clock signals adjustable rather than fixed. The delay unit's delay time is dynamically controlled by control signals from the fuse unit, allowing the system to transition between different timing states based on PVT conditions. This dynamic adjustment capability enables the circuit to adapt to environmental variations while maintaining timing accuracy.
Solution Approach 2:
The patent segments the clock signal generation into multiple controllable parts: a delay unit that can be independently adjusted, a fuse unit that generates control signals, and rising/falling internal clock signal generation paths. This segmentation allows independent optimization of each part and enables precise control over the pulse width of internal clock signals without requiring complete circuit redesign.
Data Source
AI summary
A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock signal generating circuit includes a fuse unit for generating first and second fuse signals based on fuse cutting of fuses, a control signal generating unit for generating first and second fuse signals in response to the fuse signals, a clock signal delaying unit for generating a delayed clock signal by delaying the external clock signal by a delay section specified by the control signals, and a clock generating unit for generating a first internal clock signal in synchronization with a rising edge of the delayed clock signal and for generating a second internal clock signal in synchronization with a falling edge of the delayed clock signal.