Clock Path Delay Compensation for Power Supply Timing Sensitivity
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Solution Overview
Problem
Memory devices face timing variations in clock signals due to power supply sensitivities, which can cause operational issues as different components in the clock path respond differently to voltage and current variations, leading to phase drift and synchronization problems.
Innovation Solution
A delay compensation circuit is implemented that adjusts the delay of clock signals based on phase differences detected between forward and feedback clock paths, using switch circuits and timing circuits with predictable delay power supply sensitivities to compensate for variations in power supply, ensuring the clock signals remain in phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If delay circuits are added to adjust clock signal timing, then clock signal timing can be adjusted, but timing variation increases due to power supply sensitivity
Solution Approach 1:
A feedback mechanism is implemented where the output of the delay circuit is fed back to a second input of the XOR gate. This feedback loop allows the circuit to automatically adjust and compensate for timing variations caused by power supply sensitivity, resolving the contradiction between timing adjustability and timing stability.
Solution Approach 2:
An XOR gate is introduced as an intermediary element that compares the original clock signal with the delayed clock signal. This intermediary component enables precise timing adjustment while providing a mechanism to counteract power supply sensitivity effects, thus maintaining timing reliability despite the addition of delay circuits.
2Measurement precision
If multiple delay circuits are used to achieve precise timing control, then timing control precision is improved, but the sum of timing variations from each circuit causes operational problems
Solution Approach 1:
Multiple delay circuits are merged into a single integrated delay block with feedback. By combining the delay functions and adding feedback, the circuit achieves precise timing control while the feedback mechanism compensates for the cumulative timing variations that would otherwise cause operational problems.
Solution Approach 2:
The feedback connection from the delay circuit output to the XOR gate input creates a self-correcting system. This feedback continuously monitors and compensates for timing variations accumulated through multiple delay stages, maintaining operational stability despite high timing control precision.
3Adaptability or versatility
If delay circuits with different power supply sensitivities are used, then timing adjustment flexibility is increased, but differences in response to power supply variation cause differing degrees of timing variations
Solution Approach 1:
The XOR gate serves as an intermediary that compares signals and highlights timing differences caused by varying power supply sensitivities. This allows the circuit to detect and compensate for inconsistencies, maintaining timing consistency while preserving adjustment flexibility.
Solution Approach 2:
Feedback from the delayed signal path allows the circuit to automatically compensate for differences in power supply sensitivity responses. The feedback mechanism adjusts the timing to maintain consistency across varying power supply conditions, resolving the contradiction between flexibility and consistency.
Data Source
AI summary
Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.