Receiver-Side Clock Delay Calibration for Source Synchronous Skew
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Solution Overview
Problem
In source synchronous systems, skew between clock and data signals can lead to incorrect data pulse identification, especially at higher frequencies, necessitating efficient skew correction processes that minimize overhead.
Innovation Solution
A skew correction system comprising a clock delay control circuit, data delay control circuits, and sampling circuitry that adjusts delays to position sampling transitions in target sampling positions, using adjustable delay circuits and a controller to identify and set reference and target delay amounts based on sampling errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If skew correction processes are implemented to correct skew between clock and data signals, then data pulse identification accuracy is improved, but system overhead increases
Solution Approach 1:
The system uses the existing data signals themselves to generate calibration information. By feeding data signals back through the interface and using them to drive delay elements, the system self-calibrates without requiring external test equipment or additional calibration data sources, thereby reducing overhead while maintaining accuracy.
Solution Approach 2:
The patent combines the data signal transmission path with the skew calibration path by using the same physical interface and signals for both data transfer and calibration purposes. This merging eliminates the need for separate calibration infrastructure, reducing system overhead while maintaining measurement precision.
2Productivity
If data transmission frequency is increased to improve productivity, then data transfer speed is improved, but skew-related errors increase
Solution Approach 1:
The system implements a feedback mechanism where data signals are fed back through the interface and used to monitor skew conditions. This feedback loop allows the system to detect skew-related errors in real-time and adjust calibration parameters accordingly, maintaining reliability even at high transmission frequencies.
Solution Approach 2:
The system performs skew calibration using delay elements before high-speed data transmission begins. By pre-adjusting the timing alignment of clock and data signals through programmable delay elements, the system eliminates skew-related errors before they can affect high-frequency data transfer, ensuring both productivity and reliability.
Data Source
AI summary
A skew correction system includes delay circuits positioned in front of sampling circuitry. A skew correction controller first delays an input clock signal to create hold violations. Then with, with the delay of an input clock signal fixed at a reference delay amount, the skew correction controller delays input data signals first to remove or reduce the hold violations, and then to create setup violations. Based on the delaying, the skew correction controller identifies data valid windows for the input data signals, and in turn, identifies target delay amounts that position a delayed clock signal in target sampling positions.