Adjustable Clock Network Delay for Signal Skew Compensation
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Solution Overview
Problem
Integrated circuits face clock skew issues due to manufacturing variations causing differences in signal propagation characteristics across different clock networks, leading to misalignment of clock signals at various circuit blocks.
Innovation Solution
A circuit system comprising first and second clock networks, a phase detector circuit, and a phase-locked or delay-locked loop circuit, which compares phases of clock signals to generate phase detection signals and adjusts the phase of clock signals to reduce skew between clock networks, and an integrated circuit with a signal network and adjustable delay circuits to compensate for signal skew by adjusting delays based on phase detection signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signals are transmitted through different clock networks with different signal propagation characteristics, then the integrated circuit can support larger scale and more complex designs, but clock skew and misalignment occur between circuit blocks
Solution Approach 1:
The patent applies local quality by inserting adjustable delay circuits at specific locations within the clock network (between the clock signal source and circuit blocks) to provide localized compensation for signal propagation differences. Each delay circuit can be independently adjusted to compensate for the specific characteristics of its local clock network path, thereby maintaining synchronization across the entire integrated circuit while supporting larger scale designs.
2Reliability
If manufacturing variations are reduced to maintain consistent signal propagation characteristics, then clock skew is minimized, but manufacturing cost and complexity increase
Solution Approach 1:
The patent implements self-service by providing adjustable delay circuits that can be tuned after manufacturing to compensate for process variations. Instead of requiring extremely tight manufacturing controls, the system allows post-manufacturing adjustment of delay values to achieve proper clock synchronization. This shifts the burden from manufacturing precision to post-manufacturing calibration, reducing manufacturing complexity and cost.
3Reliability
If adjustable delay circuits are added to compensate for skew, then clock synchronization is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by adjusting the delay parameter of inserted delay circuits to compensate for clock skew. Rather than redesigning the entire clock network topology, the solution modifies a single parameter (delay time) of existing or inserted components. This approach provides effective skew compensation with minimal structural changes, thereby limiting the increase in device complexity.
Data Source
AI summary
An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.