Clock-Delayed Domino Logic Circuit for Variation-Robust High-Speed Timing
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Solution Overview
Problem
Existing semiconductor logic circuits face challenges in operating at high speeds while being robust to on-chip variations, particularly in clock-delayed domino logic circuits where reliable operation is hindered by the termination of logic network evaluation during clock signal buffering.
Innovation Solution
A clock-delayed domino logic circuit is designed with a precharge circuit, evaluation circuit, logic network, and phase control circuit that control node connections based on clock signals, utilizing NMOS and PMOS transistors to determine logic levels and invert signals, thereby reducing the influence of on-chip variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock-delayed domino logic is used to achieve high-speed operation, then operating speed is improved, but reliability deteriorates due to termination of logic network evaluation during clock signal buffering
Solution Approach 1:
The logic network evaluation is completed before the clock signal is buffered and delayed. The precharge phase prepares the dynamic node, and the evaluation phase completes the logic evaluation before the clock signal enters the buffer, ensuring that all evaluations are finished before the delayed clock arrives at subsequent stages.
Solution Approach 2:
The clock-delayed domino logic circuit is divided into distinct phases: precharge phase, evaluation phase, and hold phase. Each phase has specific control signals that manage the timing of operations, separating the logic evaluation from the clock buffering to ensure reliable operation at high speeds.
2Ease of operation
If buffer is added to delay clock signal between stages, then clock timing control is improved, but device complexity increases
Solution Approach 1:
The buffer circuit serves multiple functions: it delays the clock signal to achieve proper timing between stages, it isolates the clock distribution from logic evaluation variations, and it provides signal regeneration. This multi-functionality reduces the need for separate dedicated delay circuits.
3Reliability
If logic network evaluation is terminated during clock buffering, then clock signal integrity is improved, but productivity decreases
Solution Approach 1:
The logic network operates in periodic cycles with distinct precharge and evaluation phases synchronized to the clock signal. During the evaluation phase, the logic network is active and evaluating inputs, while during the precharge phase, it is reset. This periodic operation ensures that evaluation completes before clock buffering occurs, maintaining both integrity and productivity.
Data Source
AI summary
A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.