Clock-Delayed Signal Sampling for Accurate Low-Frequency Analysis
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Solution Overview
Problem
Existing sampling circuits fail to generate a sufficiently small delay in clock signals, leading to inaccurate representation of input signals when the delay is too large, and reducing the frequency of the output signal to a lower value compared to the input signal frequency.
Innovation Solution
A device with a clock signal generator that alternates between an original clock signal and its delayed version, generating a second clock signal with a delay that allows a reduced frequency output signal to accurately represent the input signal, facilitating precise analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay in clock signals is reduced to improve sampling accuracy, then the measurement precision improves, but the device complexity increases
Solution Approach 1:
The clock signal generation is divided into multiple independent modules: a first clock signal generator, a second clock signal generator with delay element, and alternating signal generation logic. This segmentation allows precise control of delay parameters while distributing circuit complexity across modular components, resolving the contradiction between achieving small delay for accuracy and maintaining manageable device complexity.
Solution Approach 2:
The invention changes the delay parameter of the clock signal to be sufficiently small (less than one-tenth of the input signal period) while adjusting the alternating pattern between original and delayed clock signals. This parameter optimization enables accurate sampling representation without requiring excessively complex delay circuitry, as the precise delay value is achieved through controlled parameter selection rather than complex circuit design.
2Ease of operation
If the frequency of the output signal is reduced to facilitate analysis, then the ease of operation improves, but the productivity decreases
Solution Approach 1:
The sampling circuit employs periodic alternating action between original and delayed clock signals in a systematic pattern. This periodic structure allows the output signal frequency to be reduced to a manageable level for analysis while maintaining high effective sampling throughput, as the alternating pattern ensures comprehensive signal capture over time. The rhythmic switching between clock sources optimizes both analysis ease and sampling efficiency.
Solution Approach 2:
The delayed clock signal is generated in advance with a precisely controlled delay, allowing the sampling system to prepare sampling points before the actual sampling event. This preliminary action enables the output frequency to be reduced for easier analysis while maintaining accurate representation of the input signal, as the pre-prepared delayed clock signal ensures no sampling points are missed despite the lower output frequency.
Data Source
AI summary
A device includes a first clock signal generator, a second clock signal generator, an input signal generating circuit, and an input signal sampling circuit. The first clock signal generator generates a first clock signal. The second clock signal generator generates a second clock signal delayed relative to the first clock signal. The input signal generating circuit includes a voltage signal generator and a functional circuit. The voltage signal generator generates a voltage signal. The functional circuit receives the voltage signal and performs one or more circuit functions. The input signal sampling circuit samples values of the voltage signal at rising or falling edges of the second clock signal and to provide the sampled values as an output signal, whereby one or more characteristics of the voltage signal are analyzed based on the output signal.