Clock Deskew Circuit Using Intermediate Latch for Phase Offset Compensation
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Solution Overview
Problem
Existing systems face challenges in reliably transferring data between clock domains with unknown phase offsets, often requiring complex initialization routines and latch control logic, which can introduce additional delays and are not feasible with typical cell libraries.
Innovation Solution
A clock deskew circuit that includes a data path with transmitter and receiver latches and an intermediate latch, controlled by a control circuit generating a control clock based on both transmitter and receiver clocks, allowing operation in either transmitter-clock-last or receiver-clock-last modes to compensate for phase offsets, thereby ensuring safe data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FIFO buffers are used to transfer data between different clock domains, then data transfer reliability is improved, but device complexity and additional delay are introduced
Solution Approach 1:
The patent introduces an intermediate latch as a mediator component between the transmitter latch and receiver latch. This intermediate latch, controlled by a specifically timed control clock, acts as a buffer that ensures data is properly transferred between clock domains with unknown phase offsets, replacing the need for complex FIFO buffers while maintaining reliability
Solution Approach 2:
The data transfer path is segmented into distinct stages: transmitter latch, intermediate latch, and receiver latch. Each latch is controlled by its own clock signal, allowing independent timing control. This segmentation enables reliable data transfer across clock domains without requiring complex FIFO structures
2Reliability
If variable delay circuit is continuously adjusted to locate valid timing windows, then data transfer safety is improved, but initialization complexity and circuit complexity increase
Solution Approach 1:
The control circuit is pre-configured with logic that automatically generates the control clock signal with appropriate timing characteristics. The control clock is derived from both transmitter and receiver clocks through predetermined logic operations, establishing valid timing windows in advance without requiring continuous adjustment during initialization
Solution Approach 2:
The control circuit uses feedback from both the transmitter clock and receiver clock to automatically adjust and generate the control clock signal. This feedback mechanism ensures the control clock maintains proper phase relationships with both clocks, enabling safe data transfer without complex initialization routines
3Reliability
If latch control logic uses dynamic CMOS circuits or C-elements, then data transfer reliability is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent changes the control parameter from using specialized dynamic CMOS circuits or C-elements to using standard static logic gates available in typical cell libraries. The control clock generation logic is implemented using conventional logic gates with adjusted timing parameters, making the circuit manufacturable with standard processes while maintaining reliability
Data Source
AI summary
A clock deskew circuit for transferring data from a first clock domain to a second clock domain. This circuit includes a data path, which has: a transmitter latch controlled by a transmitter clock in a first clock domain; a receiver latch controlled by a receiver clock in a second clock domain; and an intermediate latch coupled between the transmitter latch and the receiver latch. The transmitter clock and the receiver clock have an unknown phase offset. The circuit additionally includes a control circuit coupled between the transmitter clock and the receiver clock, and generates a control clock for the immediate latch based on the transmitter clock and the receiver clock. The control circuit selects between a first operation mode and a second operation mode for the data path circuit based at least on the phase relationship of the control clock with respect to the transmitter clock and the receiver clock.