Duty-Cycle Phase Shift Circuit for Precise Clock De-Skew
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Solution Overview
Problem
Conventional de-skew circuits in high-density multi-lane forwarded-clock links face challenges in aligning received clocks with data efficiently, particularly in terms of duty-cycle and phase-shift accuracy, which are crucial for processor interfaces and power management.
Innovation Solution
A duty-cycle corrector phase shift (DCCPS) circuit incorporating a voltage-controlled delay line (VCDL) and digital-controlled delay line (DCDL) circuits, along with error amplifiers and DC samplers, to achieve a 50% duty cycle and precise phase shifts, such as 90 or 270 degrees, for clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If DLL or PLL is adopted in conventional de-skew circuits, then phase alignment capability is provided, but duty-cycle distortion occurs and power consumption increases
Solution Approach 1:
The patent replaces conventional DLL/PLL circuits with a de-skew circuit that uses simple delay elements and logic gates to achieve phase alignment. This substitution eliminates the complex feedback mechanisms and high-power components of DLL/PLL while maintaining the essential function of aligning clock phases with data signals.
Solution Approach 2:
The patent changes the approach from active feedback-based phase locking to passive delay-based phase shifting. By adjusting delay parameters through selectable delay elements rather than through feedback control, the circuit achieves phase alignment with reduced power consumption and without duty-cycle distortion.
2Measurement precision
If DLL or PLL is adopted in conventional de-skew circuits, then phase alignment capability is provided, but duty-cycle distortion occurs
Solution Approach 1:
The patent replaces DLL/PLL circuits with a de-skew circuit using delay elements and logic gates, eliminating the feedback mechanisms that cause duty-cycle distortion while preserving phase alignment functionality.
Solution Approach 2:
The patent divides the phase adjustment function into multiple selectable delay elements, each providing a discrete delay amount. This segmentation allows precise control of phase shift without the continuous adjustment and feedback that cause duty-cycle distortion in conventional circuits.
3Measurement precision
If conventional de-skew circuits are used, then clock alignment is attempted, but complexity and power consumption increase
Solution Approach 1:
The patent substitutes complex DLL/PLL feedback systems with a simple array of delay elements and logic gates, dramatically reducing circuit complexity while maintaining clock alignment capability.
Solution Approach 2:
The patent extracts only the essential function of phase alignment from the complex DLL/PLL system, implementing it through minimal components (delay elements and logic gates) without the unnecessary feedback and control machinery.
Data Source
AI summary
One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.