Clock Detection and Selection Circuit for Host Sync Switching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In high-speed data communication systems, devices often struggle to recognize or determine the frequency of the reference clock signal provided by the host, leading to potential communication quality degradation or failure, especially when extra negotiation mechanisms are unavailable.

Innovation Solution

An integrated circuit with clock detection and selection functionality, comprising an embedded oscillator, detection circuit, and selection circuit, which generates an embedded clock signal, detects the existence and frequency of the reference clock signal through sampling and counting operations, allowing the device to automatically synchronize with the host without additional information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the host does not provide the reference clock signal or the negotiation process relies on extra mechanisms unavailable on the device, then the device cannot recognize the frequency of the reference clock signal or determine its operating frequency, but this leads to communication quality degradation or communication failure

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidclock frequency detection difficulty
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The device performs self-detection of the reference clock signal frequency using an embedded oscillator and detection circuit. The system autonomously determines the clock frequency through sampling and counting operations without requiring external assistance or additional negotiation mechanisms from the host, thereby resolving the contradiction between communication reliability and detection difficulty

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The detection circuit acts as an intermediary between the host's reference clock signal and the device's operating frequency determination. It samples the reference clock signal, counts its cycles using the embedded oscillator as reference, and automatically determines the frequency, eliminating the need for direct host-device negotiation about clock parameters

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the device uses traditional clock detection methods requiring host provision of reference clock and extra negotiation mechanisms, then communication can be established under controlled conditions, but the device cannot quickly switch operating frequency or mode when host mode changes

Engineering Contradiction:
Improveoperating mode adaptabilityVSAvoidmode switching time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The device continuously monitors and detects the reference clock signal frequency in advance using the embedded oscillator and detection circuit. By maintaining ready knowledge of the current clock frequency through ongoing sampling and counting operations, the device can immediately switch to the appropriate operating mode when the host changes modes, eliminating negotiation delays and enabling rapid adaptation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The detection circuit provides continuous feedback about the reference clock signal frequency to the device's control logic. This feedback mechanism enables the device to automatically adjust its operating frequency and mode in real-time based on host actions, achieving quick mode switching without requiring explicit host instructions or lengthy negotiation processes

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10256801B2Integrated circuit with clock detection and selection function and related method and storage device
Publication Date: 2019.04.09 M31 TECH
  • US10256801B2 patent drawing
  • US10256801B2 patent drawing
  • US10256801B2 patent drawing

AI summary

An integrated circuit with clock detection and selection function for use in a storage device includes: an embedded oscillator, a detection circuit and a selection circuit. The embedded oscillator is configured to generate an embedded clock signal. The detection circuit includes a sampling and counting circuit and a clock determination circuit. The detection circuit, and is configured to detect existence of a reference clock signal provided by a host based on sampling and counting operations that are performed according to a signal on a clock signal lane and the embedded clock signal. The selection circuit is coupled to the detection circuit and the embedded oscillator, and is configured to select one of the embedded clock signal and the signal on the clock signal lane according to the existence of the reference clock signal as an output clock signal, thereby to provide the output clock signal to the storage device.