Clock Detector Circuit Without Reference Voltage or Auxiliary Oscillator

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Solution Overview

Problem

Existing clock detection circuits require significant circuit area and precise reference voltages for accurate detection, and digital alternatives often need an auxiliary oscillator, which may not be available in all systems.

Innovation Solution

A compact clock detector circuit using CMOS transmission gates, capacitors, and Schmitt triggers that detects clock signal toggling without requiring a comparator or reference voltage, and operates independently of an auxiliary clock source.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If an analog approach is used for clock detection, then detection accuracy is improved, but circuit area and power consumption increase

Engineering Contradiction:
Improvedetection accuracyVSAvoidcircuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent replaces the analog mechanical/comparator-based detection system with a digital logic system using D flip-flops and XOR gates. This substitution eliminates the need for precision reference voltages and analog comparators, achieving accurate clock detection through digital state comparison instead of analog voltage threshold detection.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent creates a digital copy of the clock signal state using D flip-flops that capture and hold the signal state. By comparing the current state with the previous state through XOR gates, the system accurately detects clock transitions without requiring analog reference voltages, thus reducing circuit area while maintaining detection accuracy.

Inventive Principle:
Principle #26Copying

2Area of stationary object

If a digital approach with auxiliary oscillator is used, then circuit area is reduced, but device complexity increases due to additional components

Engineering Contradiction:
Improvecircuit areaVSAvoiddevice complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the auxiliary oscillator component from the clock detection system. Instead of using an external reference oscillator to generate timing signals, the invention uses the clock signal itself and simple digital logic (D flip-flops and XOR gates) to detect transitions, thereby reducing device complexity while maintaining small circuit area.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The clock detection circuit serves itself by using the clock signal under test as the input to the D flip-flops. The circuit detects its own input signal's transitions without requiring external auxiliary components, eliminating the need for separate oscillator circuits and reducing overall device complexity.

Inventive Principle:
Principle #25Self-service

3Reliability

If an auxiliary oscillator is used to establish time window, then detection capability is improved, but adaptability decreases when oscillator is unavailable

Engineering Contradiction:
Improvedetection capabilityVSAvoidadaptability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal clock detection circuit that works with any clock signal regardless of frequency or source. The D flip-flop based design uses the clock signal itself to drive the detection logic, making the circuit adaptable to various clock sources without requiring specific auxiliary oscillators, thus improving versatility while maintaining reliable detection capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10727820B2Power- and area-efficient clock detector
Publication Date: 2020.07.28 ADVANCED MICRO DEVICES INC
  • US10727820B2 patent drawing
  • US10727820B2 patent drawing
  • US10727820B2 patent drawing

AI summary

A clock detector includes a first detector circuit, a second detector circuit, and a toggle detector circuit. The first detector circuit is for activating a first detect signal in response to detecting that a clock signal that toggles between first and second logic states when present is stuck in the first logic state, and keeping the first detect signal inactive otherwise. The second detector circuit is for providing a second detect signal in response to detecting that the clock signal is stuck in the second logic state, and keeping the second detect signal inactive otherwise. The toggle detector circuit is for activating a toggle detect signal in response to both the first detect signal and the second detect signal being inactive, and keeping the toggle detect signal inactive in response to an activation of either the first detect signal or the second detect signal.