Clock Distribution Circuit with Amplitude Amplification
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Solution Overview
Problem
Conventional clock distribution circuits face challenges in maintaining stable common-mode voltage and sufficient amplitude due to insufficient bandwidth, especially as circuit size increases and operating speeds rise, leading to increased internal delay and unsuitability for high-speed operations.
Innovation Solution
A clock distribution circuit with a transmission buffer and amplitude amplification buffer, both configured with the same topology using transistors of differing conductivity types, and including bias adjustment transistors, ensures stable common-mode voltage and amplitude during signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple-stage buffer transmission is used to distribute clock signals, then the clock signals can be provided with desired amplitude and common-mode voltage, but the bandwidth becomes insufficient and amplitude cannot be maintained at high speeds
Solution Approach 1:
The patent applies dynamics by making the buffer circuit parameters adjustable through bias voltage control. The transconductance of differential pairs and current mirror ratios can be dynamically adjusted by changing bias voltages, allowing the circuit to adapt to different operating speeds and maintain adequate bandwidth even at high frequencies while preserving common-mode voltage stability.
Solution Approach 2:
The patent changes physical parameters of the buffer circuit, specifically the transconductance values (gm1, gm2, gm3, gm4) and current mirror ratios, to optimize performance at different operating speeds. By adjusting these parameters through bias voltage control, the circuit maintains sufficient bandwidth for high-speed operation while keeping the common-mode voltage stable.
2Quantity of substance
If the number of output stages is increased to drive more loads, then more clock signals can be distributed, but the internal delay increases making the circuit unsuitable for high-speed operations
Solution Approach 1:
The patent segments the clock distribution function into multiple independent buffer circuits (first buffer circuit and second buffer circuit), each capable of driving separate load circuits. This segmentation allows parallel operation of multiple buffers, increasing the total number of output clock signals while keeping the propagation delay of each individual buffer stage manageable for high-speed operation.
Solution Approach 2:
The patent creates universal buffer circuits that can be replicated and configured to drive multiple loads simultaneously. Each buffer circuit is designed with adjustable parameters that can be optimized for different loading conditions, allowing the same circuit topology to serve multiple functions and drive numerous outputs without proportionally increasing internal delay.
3Device complexity
If conventional buffer circuits are used, then the circuit structure is simple, but the bandwidth is insufficient to maintain adequate signal amplitude at high operating speeds
Solution Approach 1:
The patent uses a composite circuit structure combining differential pairs with current mirror loads and additional amplification stages. This composite architecture integrates multiple functional elements (differential input stage, current mirror active load, and gain stages) to achieve high bandwidth and adequate signal amplitude while maintaining a relatively compact and manageable circuit structure suitable for integrated implementation.
Data Source
AI summary
A clock distribution circuit for suitably generating, transmitting, and receiving clock signals used in circuits that are configured with the same circuit topology is provided. The clock distribution circuit has a transmission buffer circuit that transmits a clock signal and an amplitude amplification buffer circuit that amplifies the amplitude of cross-coupling connections inserted in parallel with the transmission buffer circuit on a transmission path for the clock signal. Wherein the number of transistors having the same conductivity type as the transistors of a differing conductivity type of the transmission buffer circuit and that of the transistors of a differing conductivity type of the amplitude amplification buffer circuit are the same. At least one transistor is provided as a bias adjustment transistor for adjusting bias in each of the transmission buffer circuit and the amplitude amplification buffer circuit, respectively, and bias adjustments are made simultaneously.