Clock Distribution Circuit With V-T Drift Resistant Regulation

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Solution Overview

Problem

The clock distribution path in LPDDR5 memory interfaces experiences excessive re-training due to voltage and temperature drift, leading to increased power consumption and reduced throughput.

Innovation Solution

A voltage-temperature drift resistant and power efficient clock distribution circuit that operates on a regulated voltage independent of the VDD supply, using a differential amplifier, programmable resistor ladder, and converters to generate a reference voltage proportional to the threshold voltage of devices in the clock distribution path, reducing the impact of VDD supply drift and temperature variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the clock distribution path operates on VDD supply voltage, then the circuit is simple to implement, but the propagation delay becomes sensitive to voltage and temperature drift requiring excessive re-training

Engineering Contradiction:
Improvecircuit implementation simplicityVSAvoidpropagation delay stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A voltage regulator circuit is introduced as an intermediary between the VDD supply and the clock distribution path. This regulator generates a regulated voltage that is decoupled from VDD fluctuations, thereby stabilizing the propagation delay of the clock distribution path while maintaining circuit simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The voltage regulator dynamically adjusts the regulated voltage output based on temperature and process conditions to compensate for drift in the clock distribution path. By changing the voltage parameter in response to environmental conditions, the system maintains stable propagation delay without requiring re-training.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If frequent re-training is performed to compensate for voltage-temperature drift, then the propagation delay stability is maintained, but power consumption increases

Engineering Contradiction:
Improvepropagation delay stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The voltage regulator continuously provides a stabilized voltage to the clock distribution path, maintaining constant propagation delay without interruption. This continuous stabilization eliminates the need for periodic re-training operations, thereby reducing power consumption while maintaining reliability.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The voltage regulator incorporates feedback mechanisms that monitor temperature and voltage conditions, automatically adjusting the regulated voltage to compensate for drift. This closed-loop feedback system maintains propagation delay stability continuously, eliminating the need for open-loop re-training sequences and reducing overall power consumption.

Inventive Principle:
Principle #23Feedback

3Reliability

If the regulated voltage is made independent of VDD supply, then the clock distribution path becomes resistant to voltage drift, but the device complexity increases

Engineering Contradiction:
Improvevoltage drift resistanceVSAvoidcircuit component count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The voltage regulator circuit is designed to serve multiple functions: it regulates voltage for the clock distribution path, compensates for temperature drift, and operates independently of VDD fluctuations. By consolidating these functions into a single multi-functional block, the increase in device complexity is minimized while achieving voltage drift resistance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution minimizes the need for frequent re-training of the clock distribution path, reducing power consumption and improving throughput by maintaining stable propagation delay and rejecting high-frequency power supply noise.

Implementation Method 1

The voltage regulator may be configured to receive a reference voltage from the voltage generator and to generate a regulated voltage

Methodology Applied
Scientific EffectVoltage regulation:

Implementation Method 2

The voltage regulator circuit may include a differential amplifier and a power p-channel metal-oxide semiconductor ('PMOS') located between the voltage generator and the clock distribution path

Methodology Applied
Scientific EffectDifferential amplification:

Implementation Method 3

The voltage generator may include a programmable resistor ladder. The programmable resistor ladder may be in parallel with one or more threshold voltage sensing devices

Methodology Applied
Scientific EffectResistive voltage division: Electrical Resistance

Data Source

PatentUS12040798B1Clock distribution architecture
Publication Date: 2024.07.16 CADENCE DESIGN SYST INC
  • US12040798B1 patent drawing
  • US12040798B1 patent drawing
  • US12040798B1 patent drawing

AI summary

Embodiments included herein are directed towards a voltage-temperature drift resistant and power efficient clock distribution circuit. Embodiments may include a current generator and a voltage generator configured to receive an input from the current generator. Embodiments may also include a regulator which may be configured to receive a reference voltage from the voltage generator as an input and to generate regulated voltage as output. The clock distribution path may operate on a regulated voltage, the regulated voltage having a value proportional to a threshold value associated with a plurality of devices included in the clock distribution path.