Clock Distribution Architecture for Dual Core Engine Transceiver
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Solution Overview
Problem
Existing radio systems, particularly those using Dual Integrated Core Engine Transceivers, face issues with reference clock signal corruption due to noise interference, which affects RF performance and power consumption, as the same fixed frequency is applied to ADC and DAC regardless of waveform requirements.
Innovation Solution
The implementation of a clock distribution architecture that converts the incoming reference clock to a clean analog signal, routing it directly to the RF card while providing a LVDS copy to the modem, and using a programmable phase locked loop to generate clocks for RF processing, allowing frequency adjustments based on waveform needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the same reference clock signal is supplied to both core engine modem and core engine RF simultaneously, then the system operation is simplified, but the RF performance is reduced and spurious noise is increased due to noise signal corruption
Solution Approach 1:
The patent segments the clock distribution into two separate paths: a clean reference clock path to the RF circuitry and a separate digital clock path to the modem. This segmentation prevents noise from the modem from corrupting the RF reference clock, thereby resolving the contradiction between operational simplicity and RF performance reliability.
Solution Approach 2:
The patent introduces an intermediary clean reference clock signal that is derived separately from the main digital clock distribution. This intermediary signal acts as a mediator that provides the necessary clocking to RF circuitry without being corrupted by digital noise from the modem, thus maintaining both simplicity and performance.
2Device complexity
If fixed frequency clock is provided to ADC and DAC regardless of waveform requirements, then the system design is simplified, but power consumption increases when high sample rates are not required
Solution Approach 1:
The patent implements dynamic clock frequency control for the ADC and DAC, allowing the sample rate to be adjusted based on actual waveform requirements. When high sample rates are not needed, the clock frequency is reduced, thereby lowering power consumption while maintaining system design flexibility.
Solution Approach 2:
The patent changes the operational parameters of the ADC and DAC clocks dynamically, adjusting the frequency based on the specific waveform being processed. This parameter adjustment allows the system to optimize power consumption by matching the clock rate to the actual processing needs rather than running at a fixed high rate continuously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces phase noise and spurious noise in RF circuits, enhancing RF performance and optimizing power consumption by dynamically adjusting ADC and DAC clock frequencies.
Implementation Method 1
The analog 10 MHz is fed into a programmable phase locked loop chip to generate all the clocks required for RF processing
Data Source
AI summary
A method and apparatus of minimizing corruption of a reference clock to a RF circuitry in a radio system is disclosed. A DICE-T receives a reference clock in a Low Voltage Differential Signal (LVDS) format from a GVA. The DICE-T personality card converts the reference clock signal into an analog signal. The analog signal is supplied to the Core Engine RF card and the LVDS format signal is supplied to the Core Engine modem for local clocking. The Core Engine RF feeds the analog signal into a programmable phase locked loop chip to generate all the clocks required for RF processing. The analog signal is also used to provide the clocks to the ADC and DAC of core engine modem. By routing the reference clock directly to the RF card then deriving the modem clocks, the phase noise of the reference clock is reduced.