Multi-Channel Clock Distribution With Synchronous Edge Matching
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Solution Overview
Problem
Conventional multi-channel clock distribution circuits face significant phase mismatch issues due to clock signals passing through logic gates, leading to low phase matching between channels, which affects the precision and speed of time-interleaved analog to digital converters.
Innovation Solution
A multi-channel clock distribution circuit design that uses MOS transistors or CMOS transmission gates, with clock distribution sub-circuits connected in parallel, where the connection and disconnection of switches are controlled by periodic clock signals to ensure synchronous falling edges at the output, thereby improving phase matching between channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If D flip-flops are connected in series to distribute clock signals to multiple channels, then the clock distribution can be implemented, but the phase mismatch between channels increases to picosecond level
Solution Approach 1:
The clock distribution circuit is segmented into multiple independent parallel branches, each containing a switch and capacitor. This segmentation eliminates the need for series connection of D flip-flops, allowing each channel to be independently controlled while maintaining synchronous falling edges, thus resolving the phase mismatch issue while keeping the implementation straightforward.
2Ease of manufacture
If clock signals pass through logic gates with threshold voltages, then the clock distribution can be achieved, but the phase deviation between channels increases due to threshold voltage mismatch
Solution Approach 1:
The invention extracts and removes the logic gate component from the clock distribution path. By replacing the logic gate-based D flip-flop approach with a direct switch-capacitor configuration, the threshold voltage mismatch problem is eliminated entirely, as the clock signal edges are now determined by synchronous switching control rather than by logic gate threshold voltages.
Solution Approach 2:
The invention changes the controlling parameter from threshold voltage (inherent to logic gates) to externally controlled switching signals. The switches are controlled by synchronized clock signals, allowing precise control of the falling edges independent of any threshold voltage variations, thus achieving high phase matching precision.
3Device complexity
If conventional clock distribution circuits are used, then the circuit structure is simple, but the phase matching problem becomes severe as speed and precision improve
Solution Approach 1:
The invention introduces dynamic control through switches that are actively managed by synchronized clock signals. This dynamic approach allows the circuit to adapt and maintain precise phase matching across channels, overcoming the limitations of static conventional designs while keeping the overall structure relatively simple through the use of basic switch-capacitor elements.
Data Source
AI summary
A multi-channel clock distribution circuit and an electronic device includes a power source, a first switch, and at least two clock distribution sub-circuits; each clock distribution sub-circuit includes a second switch, a third switch, and a capacitor; a first end of the capacitor is connected to the power source by using the second switch and is connected to the first end of the first switch by using the third switch, a second end of the capacitor is grounded, and the first end of the capacitor is used as an output end of the clock distribution sub-circuits; and connection and disconnection of the first switch is controlled by a first clock signal, connection and disconnection of the second switch is controlled by a second clock signal, and connection and disconnection of the third switch is controlled by a third clock signal.