Clock Signal Distribution With NMOS Low-Swing Common-Mode Control
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Solution Overview
Problem
The operating speed of peripheral devices such as memories, communication devices, and graphic devices has not kept up with the speed of processors, leading to a significant speed difference, and controlling the common mode level of clock signals in phase interpolators is necessary to prevent nonlinearity and reduce jitter.
Innovation Solution
A clock signal distribution circuit using NMOS-based regulators and drivers to convert high swing clock signals into low swing clock signals, which are then input to a phase interpolator through a PMOS-based input buffer, thereby controlling the common mode level and improving linearity and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common mode level of the clock signals input to the CML-based phase interpolator is inappropriate, then nonlinearity occurs in the output and jitter increases, but controlling the common mode level requires additional circuit complexity
Solution Approach 1:
An NMOS-based driver circuit is introduced as an intermediary between the clock signal source and the CML-based phase interpolator. This driver converts high-swing clock signals into low-swing clock signals with a controlled common mode level, thereby preventing nonlinearity and reducing jitter without requiring modification of the phase interpolator itself. The driver acts as a mediator that prepares the clock signals in the appropriate form for the interpolator.
Solution Approach 2:
The driver circuit changes the parameters of the clock signals, specifically transforming them from high-swing signals to low-swing signals with a specific common mode level. This parameter transformation ensures that the clock signals meet the requirements of the CML-based phase interpolator, improving linearity and reducing jitter while maintaining circuit simplicity.
2Device complexity
If high swing clock signals are directly input to the phase interpolator, then the circuit is simpler, but nonlinearity occurs and jitter increases
Solution Approach 1:
The NMOS-based driver serves as an intermediary component that bridges the gap between the simple high-swing clock signal source and the CML-based phase interpolator. By introducing this intermediate stage, the system maintains overall simplicity while achieving the required signal conditioning for optimal interpolator performance.
Solution Approach 2:
The driver circuit performs parameter changes on the clock signals, converting them from high-swing to low-swing format with an appropriate common mode level. This transformation enables the use of simple high-swing signal sources while still achieving reliable low-swing operation at the interpolator input.
3Use of energy by moving object
If NMOS-based regulator and driver are used to convert high swing clock signals to low swing clock signals, then power consumption is reduced and linearity is improved, but the device complexity increases
Solution Approach 1:
The NMOS-based regulator and driver circuit changes the voltage parameters of the clock signals, converting them from high-swing to low-swing format. This parameter change reduces the voltage amplitude and adjusts the common mode level, resulting in lower power consumption and improved linearity. The NMOS technology inherently provides efficient voltage control and signal conversion.
Solution Approach 2:
The patent employs NMOS-based electronic circuits to replace what could be considered more power-intensive signal conditioning approaches. The NMOS driver circuit provides efficient voltage-level conversion and common mode control, substituting potential mechanical or more power-hungry electronic solutions with a compact, low-power semiconductor implementation.
Data Source
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AI summary
A clock signal distribution circuit includes an n-type metal-oxide semiconductor (NMOS)-based regulator configured to receive a first voltage and output a regulator voltage having a lower voltage level than the first voltage through a regulator voltage output node, and an NMOS-based driver including a first sub-driver configured to include first to fourth NMOS transistors and receive first and second clock signals and output first and second low swing clock signals.