Clock Distribution Network Wiring Structure for Low Skew
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Solution Overview
Problem
In high-performance integrated circuit design, existing clock distribution networks face challenges in minimizing wiring tracks, achieving low intra-net skew, and maintaining signal slew within specified margins, particularly in GHz operations, due to limitations in wire sizing and tuning methods that waste resources and complicate simulations.
Innovation Solution
The implementation of a wiring structure known as the FO structure, where two or more parallel clock signal wires are disposed in adjacent power wire bays and shorted by stubs for delay tuning, eliminating the need for wire sizing and simplifying RLC parasitic extraction, allowing for accurate simulations and flexible adaptation to meet delay and skew requirements across multiple sinks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wire sizing and tuning methods are used to meet clock skew and slew requirements, then clock distribution performance is improved, but wiring track usage increases and simulation complexity increases
Solution Approach 1:
The patent transitions from 2D planar wire routing to 3D stacked wiring layers. Multiple clock signal wires are routed in parallel across different metal layers, connected by vias. This vertical dimension allows achieving low clock skew without requiring excessive wire length adjustments in the planar domain, thereby reducing wiring track consumption while maintaining precision.
Solution Approach 2:
The clock distribution network is segmented into multiple independent clock signal wires routed in parallel across different layers. Each wire segment can be independently tuned via stub adjustments, allowing precise control of clock skew and slew without requiring extensive modification of the entire wiring structure, thus reducing overall wiring track usage.
2Manufacturing precision
If wire sizing and tuning methods are used to meet clock skew and slew requirements, then clock distribution performance is improved, but device complexity increases
Solution Approach 1:
The patent employs a universal stub structure that can be applied to any clock signal wire across different layers. This standardized component serves multiple functions: delay tuning, skew compensation, and slew rate control. By reusing the same stub design paradigm throughout the clock distribution network, the complexity of individual wire tuning is reduced while maintaining high manufacturing precision.
Solution Approach 2:
The patent controls clock distribution characteristics by changing geometric parameters of the wiring structure, specifically the length and position of stubs connected to clock signal wires. By adjusting these parameters, precise control over delay, skew, and slew rate is achieved without requiring complex active components or control circuits, thereby improving precision while managing device complexity.
3Manufacturing precision
If traditional wire tuning methods are used, then delay and skew requirements can be met, but RLC parasitic extraction accuracy decreases
Solution Approach 1:
By routing clock signals across multiple layers with well-defined via structures, the patent creates a more predictable and measurable RLC parasitic profile. The vertical interconnections provide consistent capacitance and inductance values that are easier to extract accurately compared to arbitrary planar wire routing, thereby improving measurement precision while maintaining delay and skew control.
Data Source
AI summary
A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid.