Clock Dithering Synchronization for Display Artifact Mitigation
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Solution Overview
Problem
Display artifacts such as flickering, non-uniform brightness, and color shifts occur in display devices due to clock signal interference and dithering, which varies the duration of time the display drives source lines from frame-to-frame, line-to-line, and color-to-color, causing interference with other components and systems.
Innovation Solution
Synchronizing clock dithering with display update events, such as pixel update periods or frame update periods, to maintain a uniform change in voltage across all pixels, setting the clock frequency to an integer multiple of the update rate of display lines or sub-pixels, and resetting the dithering pattern during each update period to prevent artifacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If clock dithering is applied to reduce electromagnetic interference, then interference with other components is reduced, but display artifacts such as flickering and non-uniform brightness occur
Solution Approach 1:
The patent applies periodic clock dithering where the clock frequency is varied periodically at a low frequency (e.g., 1-100 Hz) to spread electromagnetic interference spectrum while synchronizing the dithering period with display refresh cycles. This periodic variation reduces peak EMI while maintaining display uniformity by resetting the dither pattern at appropriate intervals
Solution Approach 2:
The patent implements preliminary synchronization by detecting display refresh events and resetting the clock dithering pattern at these predetermined moments. This preliminary action ensures that voltage changes across pixels remain uniform by aligning the dithering cycles with the display's natural refresh rhythm, preventing artifacts before they occur
2Object-generated harmful factors
If clock frequency is varied to spread spectrum, then electromagnetic interference is reduced, but uniformity of voltage change across pixels deteriorates
Solution Approach 1:
The patent dynamically changes clock frequency parameters within a controlled range (e.g., ±10% of nominal frequency) to spread the electromagnetic spectrum while maintaining average frequency stability. The frequency varies periodically but resets to a consistent pattern synchronized with display refresh, ensuring both spectrum spreading and voltage uniformity
Solution Approach 2:
The patent employs feedback mechanisms by monitoring display refresh events and using them to reset the dithering pattern. This feedback loop ensures that frequency variations are contained within cycles that align with display updates, maintaining voltage uniformity across pixels while achieving spectrum spreading
3Object-generated harmful factors
If dithering pattern is continuous, then electromagnetic interference is spread, but display refresh synchronization is lost
Solution Approach 1:
The patent implements periodic resetting of the dithering pattern at display refresh intervals. The clock frequency varies continuously within each refresh cycle to spread EMI, but the pattern resets at the beginning of each refresh cycle, maintaining synchronization with display updates while achieving interference spreading
Solution Approach 2:
The patent performs preliminary synchronization by detecting the start of display refresh events and initiating dithering pattern resets at these predetermined moments. This ensures that frequency variations are confined to intervals that align with display updates, maintaining both EMI spreading and refresh synchronization
Data Source
AI summary
A display device can use clock dithering to spread the frequency spectrum of the clock signal (and the signals derived therefrom) to mitigate interference with other components or systems in a host device. However, dithering the clock signal can introduce display artifacts into the display device. For example, lines or rows in the display may flicker, the brightness of display lines may be non-uniform, or color shifts in displayed pixels. To reduce display artifacts, the embodiments herein synchronize clock dithering to a display update event. That is, the display device varies a parameter of clock dithering so that the dithering is synchronized to the display update event. In another embodiment, the clock dithering is set according to the rate at which display lines or sub-pixels are updated. In another embodiment, clock dithering is synchronized to a display frame update period.