Coarse-Fine Clock Dithering for RF Spur Suppression in SoCs
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Solution Overview
Problem
Multi-radio systems-on-chip (SoCs) face interference issues due to digital circuit harmonics falling within the frequency band of RF circuits, causing degradation in RF performance and making it difficult to choose the digital clock frequency.
Innovation Solution
A clock dithering circuit is introduced, comprising a control unit, integrated clock gating cell, coarse dither unit, and fine dither unit, which generates a gated clock with reduced positive edges and applies dithering between 0 and 360 degrees to suppress harmonics, maintaining throughput above a defined threshold and being independent of PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If digital clock frequency is chosen for RF circuits operation, then RF circuits can function, but digital harmonics create spurs that degrade RF performance
Solution Approach 1:
The patent applies dynamics by making the clock frequency variable rather than fixed. The clock dithering circuit continuously varies the clock frequency around a center frequency, preventing harmonics from settling at fixed frequencies that would create persistent spurs. This dynamic frequency adjustment ensures RF circuits can operate reliably without degradation from digital noise spurs.
Solution Approach 2:
The patent changes the frequency parameter of the digital clock signal by introducing dithering. The clock frequency is modulated with small variations around a center frequency, transforming the static frequency parameter into a dynamic one. This parameter change disperses the harmonic energy across a broader frequency range, reducing peak spur levels and improving RF performance.
2Reliability
If clock dithering is applied to suppress harmonics, then RF performance improves, but timing analysis complexity increases
Solution Approach 1:
The patent applies partial dithering where only a portion of the clock signal edges are modified. By controlling the dither magnitude and duty cycle, the circuit achieves sufficient harmonic suppression while maintaining a regular enough timing pattern for static timing analysis to function. This partial action approach balances RF performance improvement with timing analysis feasibility.
Data Source
AI summary
A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.