Clock Divider Circuit for Voltage Droop Mitigation
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Solution Overview
Problem
Existing data processing devices face challenges in efficiently managing disparate operating frequencies across various data subsystems, leading to issues with rapid changes in supply current and voltage droops, which affect computational performance and maximum clock frequency.
Innovation Solution
A clock divider circuit with a transmission gate multiplexer and duty cycle adjuster is implemented to allow for gradual frequency adjustments and clock stretching, mitigating rapid changes in supply current and voltage droops by modifying enable signals and duty cycles, thereby reducing jitter and maintaining stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data subsystems operate at disparate frequencies to improve computational performance, then processing efficiency is improved, but rapid changes in supply current and voltage droops occur
Solution Approach 1:
The clock divider device dynamically adjusts the clock frequency in real-time based on system requirements, allowing data subsystems to operate at optimal frequencies while preventing rapid transitions that cause voltage droops. The device continuously monitors and modulates the clock signal to balance performance with electrical stability.
Solution Approach 2:
The invention changes the clock frequency parameter gradually rather than abruptly, using a clock divider that modulates the input clock signal to produce an output clock signal with smoothly transitioning frequency values. This prevents rapid changes in supply current that lead to voltage droops while maintaining the ability to adjust frequencies for optimal computational performance.
2Use of energy by moving object
If clock frequency is changed rapidly to adjust power mode, then power efficiency is improved, but voltage droops and di/dt issues occur
Solution Approach 1:
The clock divider device performs preliminary frequency adjustment by gradually transitioning the clock frequency before full power mode changes occur. This preliminary action prepares the system for upcoming power transitions, reducing the impact of rapid current changes and preventing voltage droops while maintaining power efficiency.
Solution Approach 2:
The invention implements cushioning against voltage droops by using a clock divider that smooths out rapid frequency transitions. The device acts as a buffer, preventing abrupt changes in clock frequency that would cause harmful di/dt effects and voltage droops, while still enabling efficient power mode adjustments.
3Reliability
If clock frequency is adjusted smoothly to prevent voltage droops, then voltage stability is improved, but frequency adjustment speed decreases
Solution Approach 1:
The clock divider device dynamically adapts its frequency adjustment rate based on system conditions. When voltage stability is critical, it smooths transitions; when rapid response is needed and conditions permit, it accelerates frequency changes. This dynamic behavior maintains voltage stability while minimizing unnecessary delays in frequency adjustment.
Data Source
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AI summary
A method for implementing clock dividers includes providing, in response to detecting a voltage drop [408] at a processor core [1 14], an input clock signal to a transmission gate multiplexer [210] for selecting between one of two stretch-enable signals. In some embodiments, selecting between the one of two stretch-enable signals includes inputting a set of core clock enable signals into a clock divider circuit [202], and modifying the set of core clock enable signals to generate the stretch- enable signals. An output clock signal is generated based on the selected stretch- enable signal.