Clock Divider Feedback Selection for Faster DLL Locking
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Solution Overview
Problem
High-speed clock signals in electronic devices pose challenges for delay-locked loops (DLLs) in determining phase relationships between delayed and reference clocks, leading to unpredictable phase relationships and longer lock times due to conventional clock divider circuits.
Innovation Solution
A clock divider circuit that provides two complementary divided clocks, allowing a phase detector to compare their phases and adjust delays more effectively, reducing the likelihood of long lock scenarios by selecting the appropriate feedback clock based on phase relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional clock divider circuits are used to divide high-frequency clocks, then clock frequency division is achieved, but the phase relationship between divided clocks becomes unpredictable and lock time increases
Solution Approach 1:
The patent implements feedback by comparing the phase relationship between divided clocks and using this comparison to select the appropriate divided clock that achieves the desired phase alignment with the reference clock, thereby reducing lock time in high-speed operations
Solution Approach 2:
The patent changes the parameter of phase relationship by providing multiple divided clocks with different phase relationships and selecting based on which phase relationship achieves lock, rather than relying on a fixed phase relationship from conventional dividers
2Measurement precision
If conventional clock divider circuits are used, then frequency division is achieved, but phase detection margin is reduced leading to longer lock scenarios
Solution Approach 1:
The patent applies dynamics by dynamically selecting between multiple divided clocks based on real-time phase relationship comparisons, allowing the system to adapt to different operating conditions and maintain adequate phase detection margin throughout the locking process
Data Source
AI summary
Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.