Clock Divider Circuit for Predictable DLL Phase Locking
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Solution Overview
Problem
High-speed clock signals in electronic devices pose challenges for delay-locked loops (DLLs) in determining phase relationships between delayed and reference clocks, leading to unpredictable phase relationships and longer-than-desirable lock times due to conventional clock divider circuits.
Innovation Solution
A clock divider circuit design that provides two complementary divided clocks, allowing a phase detector to compare their phases and adjust delays more effectively, reducing the likelihood of long lock scenarios by providing greater performance margin for phase detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional clock divider circuits are used to divide high-frequency clocks, then clock frequency division is achieved, but the phase relationship between divided clocks and reference clocks becomes unpredictable, resulting in longer lock times
Solution Approach 1:
The patent applies preliminary action by pre-establishing a known phase relationship between the divided clock and reference clock before the DLL locking process begins. The clock divider circuit is designed to output divided clocks with predictable phase relationships (e.g., 0°, 90°, 180°, or 270° phase shifts) based on the division ratio, allowing the phase detector to immediately begin accurate phase comparison without waiting for random phase alignment, thereby reducing lock time.
Solution Approach 2:
The patent employs feedback mechanisms where the phase detector continuously monitors the phase difference between the divided clock and reference clock, and this phase error information is fed back to the delay elements in the delay line. The delay elements adjust their delay characteristics based on this feedback to minimize phase error, creating a closed-loop system that accelerates the locking process by actively correcting phase mismatches rather than relying on random phase relationships.
2Productivity
If conventional clock divider circuits are used, then frequency division is achieved, but the phase relationship becomes unpredictable, requiring longer time for DLL to reach locked condition
Solution Approach 1:
The patent applies parameter changes by modifying the design parameters of the clock divider circuit to ensure predictable phase relationships. Specifically, the divider circuit is designed with controlled phase shift parameters where the phase relationship between input and output clocks is determined by the division ratio (e.g., dividing by 2 produces 0° or 180° phase shifts, dividing by 4 produces 0°, 90°, 180°, or 270° phase shifts). This parameter control ensures that the phase relationship remains predictable even at high operating speeds, thereby improving reliability without sacrificing productivity.
3Speed
If higher clock speeds are used to improve performance, then operating speed increases, but the difficulty for DLL circuits to determine phase relationship increases
Solution Approach 1:
The patent introduces an intermediary element in the form of a carefully designed clock divider circuit that acts as a mediator between the high-frequency reference clock and the DLL phase detector. This intermediary circuit divides the high-frequency clock while maintaining controlled, predictable phase relationships, effectively translating the high-speed signal into a form that is easier for the phase detector to analyze. The intermediary preserves the timing information needed for phase detection while operating at speeds compatible with the high-performance requirements.
Data Source
AI summary
Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.