Clock Divider State Machine for Constant Duty During Ratio Changes

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Solution Overview

Problem

Existing clock dividers in SoC systems face issues with maintaining a constant clock output duty ratio when the divide value changes, leading to corruption of the duty ratio and potential deterioration in clock quality.

Innovation Solution

A clock divider and division method that includes a counter, output clock generator, and state machine to manage counter expiration values, ensuring a constant clock output duty by synchronizing updates with the counter's count value and the changed divide value, thereby maintaining duty ratio consistency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the divide value of the clock divider is changed, then the clock division ratio is adjusted, but the clock output duty ratio becomes corrupted

Engineering Contradiction:
Improvedivide value change capabilityVSAvoidclock output duty ratio
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by updating the counter expiration value to the second counter expiration value (corresponding to the changed divide value) before the first counter expiration value expires. This advance update ensures that when the division ratio changes, the counter is already configured with the correct expiration value, preventing duty ratio corruption and maintaining precise clock output timing throughout the transition.

Inventive Principle:
Principle #10Preliminary action

2Speed

If the counter expiration value is updated immediately when divide value changes, then the division ratio changes quickly, but the clock duty ratio becomes inconsistent

Engineering Contradiction:
Improvedivide value change speedVSAvoidclock duty ratio consistency
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The patent implements feedback by monitoring whether the first counter expiration value has expired before updating to the second counter expiration value. This feedback mechanism ensures that the counter expiration value is updated at the appropriate moment based on the current counting state, maintaining consistent clock duty ratio while enabling quick division ratio changes. The state machine uses this feedback to determine the optimal update timing.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If the clock divider maintains constant duty ratio during divide value changes, then clock quality is preserved, but the update timing becomes complex

Engineering Contradiction:
Improveclock output duty ratioVSAvoidupdate control logic
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces a state machine as an intermediary component that manages the counter expiration value updates. This state machine simplifies the control logic by automatically monitoring the counter state and determining when to update from the first to the second counter expiration value. The intermediary handles the complexity of timing coordination, allowing the rest of the system to maintain simple, clean design while achieving precise duty ratio control during divide value transitions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260012185A1Clock divider and clock division method using same
Publication Date: 2026.01.08 ITDA SEMICON CO LTD
  • US20260012185A1 patent drawing
  • US20260012185A1 patent drawing
  • US20260012185A1 patent drawing

AI summary

A clock divider and a clock division method using the same for maintaining a constant output clock duty regardless of a divide value change timing are provided. The clock divider includes a counter configured to count an input clock to generate a counter output based on a count of a first counter expiration value corresponding to a divide value of the clock, an output clock generator configured to generate an output clock divided from the input clock according to the counter output of the counter, and a state machine configured to update the counter to a second counter expiration value corresponding to a changed divide value depending on whether the first counter expiration value has expired based on the divide value being changed.