Frequency Divider Edge Logic to Avoid Very Low Duty Cycles
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Solution Overview
Problem
Frequency dividers generate output clocks with very low duty cycles, which can lead to unreliable operation in circuits that receive these clocks, particularly when the frequency of the input clock is high and the divide ratio is small, causing errors in the timing of subsequent divide cycles.
Innovation Solution
A frequency divider design that uses a series of frequency-dividing units with a logic block to generate output clocks with synchronous edges, ensuring that the falling edges are always based on the input clock and the rising edges on the highest operational clock signal, thereby maintaining acceptable duty cycles and reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a frequency divider uses a high input clock frequency with a small divide ratio, then the output clock frequency is high, but the duty cycle becomes very low causing unreliable operation in receiving circuits
Solution Approach 1:
The frequency division operation is segmented into multiple stages with different divide ratios. Instead of using a single small divide ratio that produces very low duty cycle, the patent divides the frequency in steps (e.g., first divide by 2, then by another factor), where each stage maintains acceptable duty cycle. This segmentation allows achieving high output frequency while avoiding the harmful effect of very low duty cycle in any single stage.
Solution Approach 2:
The patent dynamically adjusts the divide ratio based on the current operating conditions. When the duty cycle approaches problematic low values, the system changes the division strategy or selects different division paths. This dynamic adaptation ensures that the duty cycle remains within acceptable ranges while still achieving the desired high output frequency, thus maintaining operation reliability.
2Device complexity
If a frequency divider uses a very low duty cycle output clock, then the circuit can be simple, but the timing of subsequent divide cycles becomes erroneous
Solution Approach 1:
The patent incorporates duty cycle correction mechanisms that prepare and adjust the clock signal before it is used for subsequent timing operations. By anticipating the potential timing errors that would result from very low duty cycles, the system pre-corrects the waveform to ensure adequate high and low periods, thereby preventing timing errors in subsequent divide cycles without significantly increasing overall system complexity.
Data Source
AI summary
A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.