Selective Clock Divider Modulation for EMI-Compliant Clock Generation
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Solution Overview
Problem
Existing clock signal generating circuits face increased production costs and complexity due to unnecessary application of spread spectrum modulation, which requires additional buffers and strict timing accuracy, even for signals not requiring EMI countermeasures.
Innovation Solution
A clock signal generating circuit that applies frequency modulation only to dividers within the integrated circuit for signals requiring EMI countermeasures, using division ratio data that fluctuates around a reference value to modulate the clock signal, thereby reducing the need for unnecessary buffers and simplifying the circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If spread spectrum modulation is applied to all clock signals in the circuit, then EMI is reduced, but production cost and circuit complexity increase due to unnecessary buffers and strict timing requirements
Solution Approach 1:
The patent applies spread spectrum modulation selectively to specific dividers within the integrated circuit based on their clock signal frequency and EMI impact, rather than uniformly to all dividers. This local differentiation reduces unnecessary complexity in circuits where EMI mitigation is not required while maintaining effectiveness where needed.
Solution Approach 2:
The patent segments the clock signal distribution network into multiple paths, applying spread spectrum modulation only to certain divider branches that require EMI countermeasures. This segmentation allows different parts of the circuit to have different modulation characteristics, reducing overall circuit complexity while maintaining EMI protection where necessary.
2Object-affected harmful factors
If spread spectrum modulation is applied to all clock signals, then EMI is reduced, but production cost increases due to additional buffers and timing accuracy requirements
Solution Approach 1:
The patent implements local quality by assessing each divider's specific requirements and applying spread spectrum modulation only where necessary. This selective approach reduces the number of additional buffers and timing control circuits needed, thereby lowering production costs while maintaining EMI reduction effectiveness.
3Object-affected harmful factors
If frequency modulation is applied to reduce energy peak level, then EMI compliance is improved, but circuit complexity increases due to modulation components
Solution Approach 1:
The patent merges the spread spectrum modulation function with the existing divider circuitry by varying the division ratio dynamically. This integration eliminates the need for separate modulation components, reducing circuit complexity while achieving EMI compliance through frequency modulation of the clock signal.
Solution Approach 2:
The patent changes the division ratio parameter of selected dividers over time to achieve frequency modulation and spread spectrum effects. By modulating this key parameter, the circuit achieves EMI reduction without requiring additional modulation hardware, thus avoiding increased circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces production costs and complexity by minimizing redundant components and maintaining timing accuracy only where necessary, effectively addressing EMI without unnecessary spread spectrum modulation.
Implementation Method 1
a frequency of the clock signal is modulated by a divider based on division ratio data that defines a division ratio of the divider
Data Source
Figure 1A
Figure 1B
Figure 2~3
AI summary
A clock signal generating circuit (100) that generates a clock signal, the clock signal generating circuit including a clock signal generator configured to generate a reference clock signal (111); and a plurality of dividers (102, 103, 104) to which the reference clock signal (111) is to be input. A division ratio of at least one of the plurality of dividers varies based on division ratio data that defines the division ratio of the at least one of the plurality of dividers. The division ratio data represents a value that fluctuates around reference division ratio data with respect to time.