Clock Signal Divider Switching for EMI-Spreading Control
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Solution Overview
Problem
Existing clock signal generators for switched mode power supplies face challenges in reducing electromagnetic interference (EMI) emissions, which often require additional design efforts and costs, and prior methods for frequency jittering are limited in flexibility and component requirements.
Innovation Solution
A clock signal generator that utilizes a plurality of frequency division factors, with a controller periodically replacing the in-use factor to spread EMI across a range of frequencies, reducing silicon area requirements and allowing for user-tunable frequency variation, thereby controlling EMI effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a single fixed frequency is used for the clock signal, then the operation is simple and stable, but electromagnetic interference (EMI) is concentrated at a single frequency causing high EMI emissions
Solution Approach 1:
The clock signal frequency is made dynamic by periodically switching between multiple frequency division factors (e.g., N1, N2, N3), transforming the static single-frequency system into a dynamic multi-frequency system that spreads EMI emissions across a frequency range rather than concentrating them at one frequency
Solution Approach 2:
The frequency division factor parameter is changed periodically between different values (N1, N2, N3), allowing the clock signal frequency to vary over time. This parameter variation effectively spreads the spectral energy of the clock signal across multiple frequencies, reducing peak EMI emissions at any single frequency
2Adaptability or versatility
If multiple oscillators are used to provide different frequencies, then frequency flexibility is improved, but silicon area increases
Solution Approach 1:
Multiple frequency generation functions are merged into a single oscillator by combining it with a frequency divider that can switch between multiple division factors. This integration eliminates the need for separate oscillators for each frequency, reducing silicon area while maintaining frequency flexibility
Solution Approach 2:
A single oscillator is made multi-functional by pairing it with a controllable frequency divider that can operate with multiple division factors (N1, N2, N3). This universal configuration allows one oscillator to effectively provide multiple frequency outputs, replacing what would traditionally require multiple dedicated oscillators
3Object-affected harmful factors
If frequency division factors are frequently switched to spread EMI, then EMI reduction is improved, but frequency stability deteriorates
Solution Approach 1:
The frequency division factor is switched periodically between different values in a controlled sequence, creating a predictable frequency modulation pattern. This periodic switching spreads EMI emissions across a frequency range while maintaining a stable average frequency and predictable timing behavior, preventing frequency instability
Solution Approach 2:
The system incorporates control logic that monitors and manages the switching between frequency division factors, ensuring that transitions occur at appropriate times and that the overall frequency behavior remains stable. This feedback control prevents chaotic frequency variations while achieving EMI spreading
Data Source
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AI summary
A clock signal generator (100) comprising an input pin (104) for receiving an oscillating signal and an output pin (106) for providing a clock signal. The clock signal generator (100) also comprises a frequency divider (110) connected between the input pin (104) and the output pin (106). The frequency divider (110) having a plurality of frequency division factors associated therewith, wherein, in use, the frequency divider (110) is configured to apply one of the plurality of frequency division factors as an in-use frequency division factor to the oscillating signal in order to generate the clock signal. The clock signal generator (100) further comprising a counter (423) configured to count the number of pulses in the output clock signal (420) and/or in the received oscillating signal, and a controller (112) configured to periodically replace the in-use frequency division factor with another of the plurality of frequency division factors when the count of the counter (423) reaches a predetermined value.