Clock Divider Circuit Using Diode-Connected FETs for Low-Power Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing AND gates and clock divider circuits consume excessive power and are slow in response to input signal changes, particularly in applications with low power budgets.
Innovation Solution
The implementation of field effect transistors and diodes in a direct connection configuration for AND gates, and a specific circuit design for clock dividers that reduces the number of loads, utilizing diode-connected transistors and FETs to enhance speed and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional AND gate configurations are used, then the circuit is simple to manufacture, but the switching speed is slow and power consumption is high
Solution Approach 1:
The AND gate is segmented into multiple parallel FET paths (direct connection path and diode-connected path) that operate simultaneously. This segmentation allows the circuit to achieve fast switching through the direct path while maintaining proper logic levels through the diode-connected path, resolving the contradiction between speed and complexity.
Solution Approach 2:
Diode-connected FETs are introduced as intermediary elements that mediate between the direct FET connection and the output. These intermediaries provide the necessary logic level control and signal conditioning without significantly impacting the switching speed, thus resolving the speed-complexity tradeoff.
2Use of energy by moving object
If conventional AND gate configurations are used, then the circuit structure is simple, but power consumption is excessive
Solution Approach 1:
The circuit utilizes the periodic switching nature of digital signals to activate different FET paths at different times. During switching transitions, the direct connection path provides fast switching with low power, while during stable states, the diode-connected path maintains proper logic levels, achieving low overall power consumption.
Solution Approach 2:
The invention changes the operational parameters of the FETs by configuring them in different modes (direct connection vs. diode-connected). This parameter change allows the same FETs to serve multiple functions - fast switching and logic level control - thereby reducing power consumption without significantly increasing circuit complexity.
3Speed
If fast switching is achieved through direct FET connection, then switching speed improves, but power consumption increases
Solution Approach 1:
The current path is segmented into multiple parallel FET configurations. The direct connection FETs provide the fast switching path with minimal resistance, while the diode-connected FETs provide an alternative path that consumes less power during steady states. This segmentation resolves the contradiction by allowing fast switching only when necessary.
Solution Approach 2:
The circuit dynamically switches between different FET paths based on the input signal state. During transitions, the direct connection path is activated for fast switching. During stable states, the diode-connected path is utilized for lower power consumption. This dynamic behavior resolves the speed-power contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution results in faster AND gates and clock dividers that operate with significantly reduced power consumption, enabling efficient clock division even in low power environments.
Implementation Method 1
a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal
Implementation Method 2
first and second diodes, each having a respective first terminal and a respective second terminal, and having a forward conduction direction from the respective second terminal to the respective first terminal
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
An AND gate comprises:a first input;a second input;an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output. Also disclosed is a clock divider stage for receiving a first clock signal oscillating at a first frequency and a second clock signal, the second clock signal being an inversion of the first clock signal, and generating a first output clock signal oscillating at half of the first frequency.