Clock Divider Synchronization for Variable Core and Fixed Peripheral Rates
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Solution Overview
Problem
Existing clock signal generation systems in automotive electronic systems face challenges in reducing power consumption while maintaining synchronization between variable clock rates for microcontroller cores and peripheral components, often requiring additional synchronizer logic and increasing complexity.
Innovation Solution
A clock signal generation system comprising a clock signal generating circuit, a divider circuit, and a controller module that allows for the selection of a variable first clock rate while maintaining a constant second clock rate for peripheral components, using a fractional divider to synchronize the clock signals and reduce power consumption without the need for additional synchronizer logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock rate applied to the microcontroller core is reduced to reduce power consumption, then power consumption is reduced, but the clock rate of peripheral components must also be reduced which may not be acceptable if constant clock rate is required
Solution Approach 1:
The clock signal generation is segmented into two independent paths: one for the microcontroller core with variable clock rate, and another for peripheral components with constant clock rate. The divider circuit separates the clock distribution function, allowing independent control of clock rates for different system components.
Solution Approach 2:
The divider circuit serves multiple functions: it divides the variable microcontroller clock to generate a constant peripheral clock, and also provides synchronization between the two clock domains. This multi-functional approach eliminates the need for separate clock generators and synchronizer circuits.
2Reliability
If additional clock generating circuits and synchronizer logic circuits are added to maintain constant peripheral clock rates, then constant clock rate for peripherals is maintained, but device complexity increases
Solution Approach 1:
The clock generation and synchronization functions are merged into a single divider circuit. This circuit simultaneously performs clock division to maintain constant peripheral clock rates and synchronization to keep peripheral clocks aligned with the variable microcontroller clock, eliminating the need for separate synchronizer logic circuits.
Solution Approach 2:
The divider circuit is designed to perform multiple functions: clock division for maintaining constant peripheral clock rates, and synchronization for keeping peripheral clocks in sync with the microcontroller clock. This universal circuit replaces what would traditionally require multiple separate components.
3Use of energy by moving object
If the clock rate is reduced to reduce power consumption, then power consumption is reduced, but computing efficiency and thermal handling are affected
Solution Approach 1:
The system implements dynamic clock rate adjustment for the microcontroller core based on operational requirements. The clock rate can be varied in real-time to optimize between power consumption and computing efficiency, allowing the system to adapt its performance characteristics to current workload demands.
Solution Approach 2:
The clock distribution system is segmented to allow independent clock rate control for the microcontroller core versus peripheral components. This enables the core to operate at optimal variable clock rates for computing efficiency while peripherals maintain stable constant rates, achieving both power savings and performance optimization.
Data Source
AI summary
A clock signal generation system is provided that includes a clock signal generating circuit arranged to provide a first clock signal having a selectable first clock rate; a divider circuit connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal.