Clock Divider Multiplexing for Glitch-Reduced Frequency Switching
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Solution Overview
Problem
In integrated circuit systems, the use of multiple clock domains to manage power and performance is hindered by significant power consumption in clock generating circuitry and the generation of undesirable 'glitches' during frequency transitions, which affects the performance of functional blocks.
Innovation Solution
A clock generation circuitry comprising a plurality of clock divider circuits and a multiplex circuit that divides the base clock signal by various divisors and selects the appropriate output to be coupled to functional blocks, with an optional phase-locked loop to generate the base clock signal, reducing power consumption and minimizing glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock divider circuits are used to provide multiple clock frequencies, then adaptability is improved, but device complexity increases
Solution Approach 1:
The clock generation circuitry is segmented into multiple independent clock divider circuits (202, 204, 206), each configured to divide the base clock signal by a specific divisor to generate a predetermined clock frequency. This segmentation allows each divider to be optimized for a specific frequency requirement while maintaining overall system adaptability.
Solution Approach 2:
The phase-locked loop (200) serves as a universal base clock generator that can support multiple clock divider circuits simultaneously. By generating a single base clock signal that feeds multiple dividers, the PLL provides multi-functional capability, enabling the system to achieve various clock frequencies through combination rather than requiring separate generation circuits for each frequency.
2Adaptability or versatility
If multiple clock domains are employed to manage power and performance, then power management capability is improved, but power consumption of clock generating circuitry increases
Solution Approach 1:
Multiple clock divider circuits are merged into a single clock domain hierarchy under one phase-locked loop. Instead of having separate clock generation circuits for each frequency domain, the design combines them into a unified structure where one PLL feeds multiple dividers, reducing redundant circuitry and overall power consumption while maintaining the ability to manage multiple power domains.
Solution Approach 2:
The phase-locked loop generates a base clock signal in advance that is then distributed to multiple clock divider circuits. This preliminary generation of the base clock allows downstream dividers to operate at lower power since they only need to perform frequency division rather than full clock generation, reducing the power consumption of the overall clock generation system.
3Adaptability or versatility
If clock frequency is changed responsive to variations in demand, then adaptability is improved, but glitches during frequency transitions occur
Solution Approach 1:
Multiple clock divider circuits are pre-configured with different division ratios to generate various clock frequencies in advance. When frequency adjustment is needed, the system can switch between pre-configured dividers rather than dynamically reconfiguring a single divider, which reduces transition glitches by avoiding mid-switching frequency instability.
Solution Approach 2:
The system dynamically selects among multiple clock divider circuits based on current frequency requirements. By implementing dynamic switching capability that can rapidly transition between pre-configured dividers, the system achieves frequency adaptability while minimizing glitch duration and impact on functional blocks.
Data Source
AI summary
Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.