Frequency Divider Clock Inversion for Stable Phase Alignment
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Solution Overview
Problem
Frequency divider circuits struggle to maintain a consistent phase relationship between multiple clock signals, especially when input clock signals become unstable due to noise, leading to unpredictable phase relationships between frequency-divided clock signals.
Innovation Solution
A frequency divider circuit comprising a first frequency dividing circuit, a second frequency dividing circuit, a detection circuit, and a selection circuit that detects the phase relationship between the frequency-divided clock signals and selects one of the signals or its inverted version to maintain a desired phase relationship.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional frequency divider circuit is used to divide multiple clock signals, then the frequency division function is achieved, but the phase relationship between the frequency-divided clock signals becomes unpredictable when input clock signals become unstable due to noise
Solution Approach 1:
The patent employs a detection circuit that continuously monitors the phase relationship between frequency-divided clock signals and provides feedback to a selection circuit. When phase inconsistency is detected (indicating input clock instability), the selection circuit switches to an alternative signal path to maintain the desired phase relationship. This closed-loop feedback mechanism ensures reliable phase relationship consistency despite noise influence on input clocks.
Solution Approach 2:
The patent dynamically switches between different signal paths based on the stability of input clock signals. The selection circuit can choose between directly using the frequency-divided clock signal or using an inverted version of the signal, depending on the detected phase relationship. This dynamic adaptation allows the system to maintain reliable phase relationships even when input clocks are affected by noise.
2Reliability
If control logic is added to maintain phase relationships, then phase consistency is improved, but circuit complexity increases
Solution Approach 1:
The patent segments the frequency division function into multiple independent frequency divider circuits, each handling one clock signal. This allows parallel processing of multiple clock signals without interfering with each other's phase relationships. The detection and selection functions are further segmented into separate dedicated circuits, making the overall system more modular and manageable despite the increased complexity.
Solution Approach 2:
The patent introduces a detection circuit as an intermediary that monitors phase relationships and provides information to a selection circuit. This intermediary layer simplifies the control logic by separating the detection function from the selection function, making the overall circuit more structured and easier to design despite the added complexity for maintaining phase consistency.
Data Source
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AI summary
A frequency divider circuit includes: a first frequency dividing circuit (10) configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit (20) configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit (30) configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit (50) configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit. The selection circuit selects and outputs one of the second frequency-divided clock signal and the inverted signal of the second frequency-divided clock signal, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit, thereby making it possible to generate and output a frequency-divided clock signal based on the second clock signal maintaining a desired phase relationship with respect to the first frequency-divided clock signal.