Clock Divider Level Correction for Temperature-Stable Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock generating circuits fail to maintain a consistent time difference between the reference clock and the divided clock due to temperature variations, leading to unsatisfied timing requirements in downstream circuits.
Innovation Solution
A clock generating circuit with a dividing unit and a distribution unit, where the dividing unit includes one or more amplifiers, dividing circuits, and a correction circuit to correct the input clock level, ensuring the divided clock's frequency is 1/N times that of the reference clock, and the correction circuit mitigates level variations caused by temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a reference clock is divided to generate a divided clock using conventional dividing circuits, then the divided clock frequency is reduced to 1/N times of the reference clock, but temperature variation causes gain variation in amplifiers and delay period variation, failing to satisfy timing requirements
Solution Approach 1:
The patent introduces a feedback mechanism where the delay period variation is detected and compensated by adjusting the reference clock phase. The system monitors the timing difference between reference clock and divided clock, and uses feedback control to correct phase shifts caused by temperature variation, ensuring timing requirements are continuously satisfied.
Solution Approach 2:
The patent changes the operating parameters of the amplifier by introducing a temperature compensation circuit that adjusts the amplifier's gain and delay characteristics based on temperature. This parameter adjustment compensates for temperature-induced variations, maintaining stable delay period and satisfying timing requirements across different temperature conditions.
2Strength
If amplifiers are used in the dividing circuit to amplify the clock signal, then the clock signal level is maintained, but temperature variation causes gain variation leading to delay period variation
Solution Approach 1:
The patent employs feedback control to monitor the amplifier's output signal and adjust its operating point. The feedback mechanism detects delay period variations caused by temperature-induced gain changes and automatically adjusts the amplifier parameters to compensate, maintaining stable delay period while preserving signal strength.
Solution Approach 2:
The patent implements temperature compensation by dynamically changing the amplifier's operating parameters such as bias current and gain settings. These parameter adjustments counteract temperature effects, ensuring that both signal level and delay period remain stable despite temperature variations.
Data Source
AI summary
A clock generating circuit includes a dividing unit and a distribution unit. The dividing unit divides a reference clock to generate a divided clock, and the divided clock has a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more. The distribution unit distributes the reference clock to a first route and a second route, the first route includes an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, and the second route includes the dividing unit. The dividing unit includes one or more amplifiers, one or more dividing circuits, and a correction circuit. The correction circuit is disposed between the amplifier and the dividing circuit, and the correction circuit corrects a level of an input clock input to the dividing circuit.