Multi-Phase Clock Divider Using Latch Loops for Phase Accuracy
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Solution Overview
Problem
Existing clock generation systems face challenges in reliably producing a family of clocks with prescribed phase shifts, particularly for high-order harmonic mixers, which can lead to phase uncertainty and increased system cost due to the need for higher VCO frequencies and power consumption.
Innovation Solution
A system and method for clock generation using a plurality of latch pairs configured to form a loop with differential clock pairs of the same frequency but with staggered phases, specifically designed for a divide-by-2 divider to generate clocks with phase shifts of 0°, 45°, 90°, 135°, 0°, 60°, and 120°, addressing phase uncertainty and reducing system complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional mixer is used to convert RF signals, then the signal can be converted to IF frequency, but interference signals are also converted to IF frequency causing signal-to-interference ratio degradation
Solution Approach 1:
The patent changes the operating parameters of the mixer by tuning it to operate at a frequency (e.g., 2.4 GHz) that is not an integer multiple of the channel spacing (e.g., 200 kHz). This parameter change ensures that interference signals from adjacent channels do not fall at the same frequency as the desired signal after mixing, thereby improving signal-to-interference ratio without requiring additional filtering components.
2Adaptability or versatility
If higher VCO frequency is used to reduce tuning range, then the tuning range can be reduced from 100% to 50%, but power consumption increases
Solution Approach 1:
The patent employs a dynamically tunable VCO that can operate across a wide frequency range (e.g., 2.0 GHz to 4.0 GHz) rather than being fixed at a higher frequency. This dynamic operation allows the system to achieve the required 100% tuning range while maintaining lower power consumption by operating at optimal frequencies for each channel, avoiding the continuous high power consumption that would result from using a fixed higher VCO frequency.
3Ease of operation
If two-stage dividers are used to generate clocks with 0°, 45°, 90°, and 135° phase shifts, then the required clocks can be generated, but phase uncertainty occurs
Solution Approach 1:
The patent introduces an intermediary phase calibration mechanism that measures and compensates for phase shifts in the clock generation circuitry. By using a calibration routine that detects actual phase relationships and adjusts timing accordingly, the system achieves precise phase alignment (within a fraction of a degree) despite the inherent uncertainties in multi-stage divider circuits.
4Ease of operation
If divide-by-4 divider is used when only divide-by-2 is needed, then clock generation is achieved, but system cost increases
Solution Approach 1:
The patent segments the clock generation function into modular components that can be independently configured. Instead of always using a divide-by-4 divider, the system can select between divide-by-2 and divide-by-4 configurations based on the specific application requirements. This segmentation allows the system to use the simpler and less expensive divide-by-2 configuration when sufficient, while only employing the more complex divide-by-4 configuration when actually needed, thereby reducing overall system cost.
Data Source
AI summary
A system and method of clock generation to provide divided-by-2 clocks with prescribed phase shifts are disclosed. In a communication system with high-order harmonic mixing, the system requires LO signals with a set of prescribed phase shifts, such as 0°, 45°, 90°, and 135°, or 0°, 60° and 120°. Often, the clock generation system involves a divide-by-2 divider to derive the clock signals with the prescribed phase shifts. In a conventional implementation of the divide-by-2 divider, the system is subject to phase uncertainty in the output signal. Accordingly, a system comprises multiple latch pairs and respective differential clocks are used to generate the clocks with the set of correct prescribed phase shifts.