Clock Divider Reset Scheme for Multi-Phase Memory Clocks
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Solution Overview
Problem
Integrated circuits face challenges in efficiently utilizing high-frequency external clock signals due to high power consumption, precision issues, and vulnerability to noise, and prior dividing circuits struggle to generate divided clock signals with target phases.
Innovation Solution
A dividing circuit system comprising a first and second dividing circuit that perform asynchronous reset operations based on a reset control signal, generating divided clock signals with different phases from both positive and negative clock signals, allowing for stable operation with high-frequency external clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the integrated circuit receives a high-frequency external clock signal to perform operations faster, then the operation speed is improved, but the power consumption increases and the circuit becomes vulnerable to noise
Solution Approach 1:
The patent divides the high-frequency external clock signal into multiple lower-frequency internal clock signals using dividing circuits. This segmentation allows the circuit to operate at high speed when needed while using lower frequency clocks for routine operations, thereby reducing power consumption during normal operation while maintaining the capability for high-speed operation when required.
2Speed
If the integrated circuit receives a high-frequency external clock signal, then the operation speed is improved, but the precision of receiving and utilizing the clock signal deteriorates
Solution Approach 1:
The patent segments the high-frequency external clock signal into multiple lower-frequency internal clock signals through dividing circuits. This segmentation improves reception precision because lower frequency signals are easier to receive and process accurately, while still enabling high-speed operation when multiple divided clocks are coordinated together.
3Speed
If the integrated circuit receives a high-frequency external clock signal, then the operation speed is improved, but the vulnerability to noise increases
Solution Approach 1:
The patent divides the high-frequency external clock signal into multiple lower-frequency internal clock signals. This segmentation reduces noise vulnerability because lower frequency signals are less susceptible to noise interference, while the system maintains high-speed operation capability through coordinated use of multiple divided clock signals.
Solution Approach 2:
The dividing circuits act as intermediary components between the high-frequency external clock signal and the internal circuit operations. These intermediaries transform the high-frequency signal into multiple lower-frequency signals, thereby reducing noise vulnerability while enabling high-speed operation.
4Ease of operation
If a prior art dividing circuit performs reset operation synchronized to internal clock signal, then the circuit operation is simplified, but it becomes impossible to generate divided clock signal with target phase
Solution Approach 1:
The patent employs resetting circuits that perform reset operations autonomously based on the clock signals themselves, without requiring external synchronization control. This self-service approach maintains operational simplicity while enabling precise phase control of the divided clock signals, as each dividing circuit independently manages its own reset timing based on its input clock signal.
Data Source
AI summary
A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.