Multi-Stage Clock Divider Switching for Lower Power Output Clocks
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Solution Overview
Problem
In electronic systems, the power consumption of clock dividers is high due to the frequency of the input clock signal, leading to increased heating and reduced battery life in devices.
Innovation Solution
A system comprising a first clock divider and a second clock divider that selects a second divider input clock signal from the input clock signal and the first divider output clock signal to provide an output clock signal of a lower frequency, reducing power consumption by optimizing the frequency ratio and using a multiplexer to select the appropriate input signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a clock divider receives a high-frequency input clock signal to provide a lower-frequency output clock signal, then the output clock signal frequency is reduced, but the power consumption of the clock divider increases proportionally to the input frequency
Solution Approach 1:
The patent divides the clock division function into multiple stages. Instead of using a single clock divider that directly divides the high-frequency input clock to the target low frequency, the system uses a first clock divider to divide the input clock to an intermediate frequency, then uses a second clock divider to further divide to the final output frequency. This segmentation allows each divider to operate at more efficient frequency ratios, reducing total power consumption.
Solution Approach 2:
The first divider output clock signal serves as an intermediary signal between the high-frequency input clock and the low-frequency final output. By introducing this intermediate frequency signal, the system avoids the power-consuming operation of directly dividing a high-frequency clock by a large factor in a single stage.
2Adaptability or versatility
If multiple clock dividers are used to provide different frequency divisions, then versatile clock signal generation is achieved, but the overall power consumption and device complexity increase
Solution Approach 1:
The second clock divider is designed to accept multiple possible input signals (both the original input clock signal and the first divider output clock signal) and select the appropriate one based on the required output frequency. This multi-functionality allows a single divider to serve multiple division ratios, reducing the total number of dividers needed while maintaining versatility.
Solution Approach 2:
The system dynamically selects which clock signal to feed into the second divider based on the required output frequency. A selection mechanism (such as a multiplexer or control logic) determines whether to use the input clock signal or the first divider output as the second divider's input, allowing the system to adapt to different frequency requirements optimally.
Data Source
AI summary
A system for providing an output clock signal, the system includes: (a) a first clock divider, adapted to receive an input clock signal and to provide a first divider output clock signal having a frequency that is lower than a frequency of the input clock signal; and (b) a second clock divider, adapted to select a second divider input clock signal out of the input clock signal and the first divider output clock signal, and to provide the output clock signal having a frequency that is lower than the frequency of the second divider input clock signal.