Clock Frequency Divider with Selective Pulse Masking for Stable Communication
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Solution Overview
Problem
Existing clock frequency divider circuits face difficulties in performing proper communication with circuits operating at different frequencies, leading to communication performance deterioration and high power consumption in clock tree circuits.
Innovation Solution
A clock frequency divider circuit that generates an output clock signal by subtracting (S−N) clock pulses from S clock pulses based on a frequency division ratio of N/S, using a control circuit to preferentially mask clock pulses at timings other than communication timings, and a processing circuit to generate the output clock signal, thereby ensuring proper communication and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock frequency divider circuits are used to distribute clock signals with different frequencies to functional blocks, then frequency division capability is improved, but communication performance deteriorates when circuits operate at different frequencies
Solution Approach 1:
The patent changes the parameter of clock pulse masking strategy by introducing communication timing information. The control circuit selectively masks clock pulses based on whether they occur at communication timings or not, transitioning from uniform masking to selective masking that preserves communication integrity while achieving frequency division.
2Stability of the object's composition
If clock tree circuits are used to reduce clock skew, then distribution uniformity is improved, but power consumption increases
Solution Approach 1:
The patent extracts the frequency division function from the clock tree circuit and places it in a separate clock frequency divider circuit. This allows the clock tree to operate at a single frequency with optimized power consumption, while frequency division is performed independently, separating the two functions that were previously combined.
3Manufacturing precision
If uniform clock pulse masking is applied for frequency division, then frequency division ratio accuracy is improved, but communication timing integrity deteriorates
Solution Approach 1:
The patent applies different masking qualities to different clock pulses based on their timing characteristics. Communication timing pulses are protected from masking while non-communication timing pulses are subject to masking for frequency division, creating local differentiation in masking behavior that preserves both accuracy and communication integrity.
Data Source
AI summary
To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S−N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal.