Clock Divider Synchronization With Scaled Pulse Width
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Solution Overview
Problem
Existing electronic systems with multiple clocked components face challenges in adjusting the root clock signal due to different divider settings and output options in component clock dividers, leading to potential disruptions in clock synchronization across sub-systems.
Innovation Solution
The proposed electronic circuit includes an oscillator circuit, a divider circuit, a synchronization control circuit, and a peripheral circuit, where the synchronization control circuit generates a synchronization pulse with a width based on the divisor value, allowing for synchronized changes in divisor values across different clock dividers while dynamically adjusting the power supply voltage to ensure proper clock propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the root clock signal is adjusted to increase power flexibility, then power flexibility is improved, but clock synchronization across different component clock dividers is disrupted
Solution Approach 1:
The system performs preliminary actions by setting up synchronization pulses with appropriate widths before adjusting the root clock signal. The synchronization control circuit generates pulses with widths calculated based on the current divider ratio, ensuring that all clock dividers are properly synchronized before any clock signal adjustments occur. This preliminary synchronization prevents disruption when power flexibility adjustments are made.
Solution Approach 2:
The synchronization control circuit acts as an intermediary between the root clock signal and the various component clock dividers. It generates synchronization pulses that mediate the relationship between the root clock adjustments and the divided clock signals, ensuring that changes in root clock frequency or divider ratios do not cause synchronization disruptions across different components.
2Device complexity
If a fixed width synchronization pulse is used, then the circuit is simple, but narrow pulses may be lost or not properly recognized by clock dividers
Solution Approach 1:
The synchronization pulse width is made dynamic rather than fixed. The synchronization control circuit calculates and generates pulse widths that adapt to the current divider ratio settings. When divider ratios change, the pulse width automatically adjusts to maintain appropriate recognition levels, ensuring reliable synchronization without requiring overly complex fixed-width pulse generation circuitry.
Solution Approach 2:
The system changes the parameter of synchronization pulse width based on the divider ratio. By dynamically adjusting this parameter, the system ensures that synchronization pulses remain wide enough to be properly recognized by clock dividers regardless of the current division setting, while avoiding the need for excessively complex circuit design.
3Reliability
If the synchronization pulse width is increased to ensure recognition, then pulse recognition reliability is improved, but the time required for synchronization increases
Solution Approach 1:
The synchronization pulse width is dynamically optimized rather than uniformly increased. The control circuit calculates the minimum necessary pulse width based on the current divider ratio, generating pulses that are just wide enough to ensure reliable recognition. This dynamic adjustment maintains high recognition reliability while minimizing the time cost of synchronization operations.
Data Source
AI summary
An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.