Clock Frequency Divider Using Pulse Subtraction for Stable Communication
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Solution Overview
Problem
Existing clock frequency divider circuits face challenges in performing proper communication with circuits operating at different frequencies, leading to communication performance deterioration and high power consumption in clock tree circuits.
Innovation Solution
A clock frequency divider circuit that generates an output clock signal by subtracting (S−N) clock pulses from S clock pulses based on a frequency division ratio of N/S, with a control circuit prioritizing clock pulse subtraction at non-communication timings, and a processing circuit generating the output clock signal accordingly, while also incorporating a clock tree circuit for distributed frequency division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock frequency division is performed by subtracting clock pulses, then frequency division ratio can be flexibly controlled, but communication timing with circuits operating at different frequencies deteriorates
Solution Approach 1:
The control circuit pre-determines which clock pulses to subtract based on communication timing information before the actual frequency division operation. By advance planning the pulse subtraction pattern around communication timing, the circuit ensures that communication occurs at guaranteed clock edges while achieving flexible frequency division ratios.
2Reliability
If clock tree circuits are used to distribute clock signals, then clock skew is reduced, but power consumption increases
Solution Approach 1:
The clock distribution is segmented into two parts: a simplified clock tree for basic distribution and local frequency divider circuits at each block for final frequency generation. This segmentation allows the clock tree to operate at lower frequencies reducing power, while local dividers provide the needed frequency variations without requiring a complex high-frequency clock tree throughout the entire system.
Solution Approach 2:
The system uses periodic clock signal generation at each functional block through local frequency dividers, rather than continuous distribution of a single high-frequency clock signal through a large clock tree. This periodic local generation reduces the burden on the clock tree and associated power consumption.
3Speed
If high-frequency clock signals are distributed throughout the system, then communication speed is improved, but clock skew increases
Solution Approach 1:
Each functional block has its own local frequency divider circuit that generates clock signals specifically tailored to that block's requirements. This local quality approach allows each block to operate at optimal frequency while the main clock tree operates at a standardized, lower frequency that minimizes skew, resolving the contradiction between speed and skew.
Data Source
AI summary
To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S−N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal.