Clock Divider Ratio Switching for Memory-Speed and Power Balance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed semiconductor integrated circuits face increased power consumption when operating at frequencies matching high-speed memories, and vice versa, leading to suboptimal performance and power management.
Innovation Solution
A clock signal generating circuit with multiple frequency division ratios that can be independently set and switched, allowing for synchronized adjustment of clock signal frequencies to match the requirements of both high-speed memories and processors, thereby controlling power consumption and maintaining high-speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor integrated circuit is operated at the operating frequency of the high-speed memory, then the memory can operate normally, but the power consumption of the semiconductor integrated circuit increases
Solution Approach 1:
The patent divides the clock signal generation system into multiple independent frequency dividing circuits, each capable of operating at different frequency division ratios. This allows the semiconductor integrated circuit and high-speed memory to be supplied with independently controlled clock signals, enabling the memory to operate at its required high frequency while the processor operates at a lower frequency to reduce power consumption.
Solution Approach 2:
The patent implements dynamic frequency division ratio switching capability, allowing the frequency division ratios to be changed based on operational requirements. The switching means enables transition between different frequency division ratios synchronously with the reference clock signal, providing flexible adaptation to different operating conditions and power management scenarios.
2Use of energy by moving object
If the high-speed memory is operated at the operating frequency of the semiconductor integrated circuit to reduce power consumption, then power consumption decreases, but the memory does not operate normally
Solution Approach 1:
The patent divides the clock signal generation system into multiple independent frequency dividing circuits, each capable of operating at different frequency division ratios. This allows the memory to receive a clock signal at its required operating frequency independent of the processor's frequency, ensuring normal memory operation while enabling power reduction in the processor.
Solution Approach 2:
The patent applies different frequency division ratios to different parts of the system - the processor and the memory - according to their specific operational requirements. This localized frequency control ensures that each component operates at its optimal frequency, with the memory receiving higher frequency clock signals for normal operation while the processor operates at lower frequencies for reduced power consumption.
3Device complexity
If a single clock signal frequency is used for both the semiconductor integrated circuit and high-speed memory, then the system is simple to control, but power consumption increases and performance is suboptimal
Solution Approach 1:
The patent segments the clock signal distribution system into multiple independent frequency dividing circuits, each with its own frequency division ratio control. This segmentation enables independent frequency control for different system components, allowing optimized power management and performance while maintaining relatively simple control architecture through standardized frequency division mechanisms.
Solution Approach 2:
The patent employs multiple frequency dividing circuits that can function independently to serve different components. Each frequency dividing circuit can operate with different division ratios, providing universal frequency adaptation capability that supports both simple control scenarios and optimized performance scenarios without requiring fundamentally different control mechanisms.
Data Source
AI summary
A clock signal generating circuit is disclosed. The clock signal generating circuit includes: a reference clock signal generating unit for generating a reference clock signal; a plurality of frequency dividing units for carrying out frequency dividing of the reference clock signal and outputting frequency-divided clock signals; a plurality of frequency division ratio storing units for storing frequency division ratios different from each other for the respective frequency dividing units; and a switching unit for switching, synchronously with the reference clock signal, at least one initial frequency division ratio at the frequency dividing units to the frequency division ratios stored in the corresponding frequency division ratio storing units.