Programmable Clock Divider Reset Paths for Faster Ripple Counting
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Solution Overview
Problem
Ripple counters in digital circuitry face challenges with slow operation and high power consumption due to propagation delays and inefficiencies in resetting and loading new count values, which hinder high-speed applications.
Innovation Solution
A programmable clock divider with multiple reset circuits and parallel data loading techniques is introduced, featuring a first flip-flop with a clock input and reset input, and a second reset circuit that provides an asynchronous reset signal to ensure efficient resetting and pre-loading of flip-flops, reducing power consumption and minimizing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If ripple counter is used for frequency division, then power consumption is reduced compared to synchronous counters, but operation speed becomes slow due to propagation delays
Solution Approach 1:
The patent implements preliminary action by pre-loading the next count value into the flip-flops before the current count is complete. The parallel data loading feature allows the counter to be pre-programmed with the next value, and the multiple reset circuits are prepared in advance to ensure immediate reset when needed, eliminating waiting time and reducing overall operation delays.
Solution Approach 2:
The patent segments the reset operation into multiple independent reset circuits, each capable of resetting specific groups of flip-flops. This segmentation allows different parts of the counter to be reset independently and in parallel, reducing the overall reset time and improving operation speed while maintaining the power-efficient ripple counter architecture.
2Reliability
If ripple counter reaches count limit, then reset operation is required, but reset and load operations introduce minimum delays that hinder high-speed operation
Solution Approach 1:
The patent maintains continuity of useful action by ensuring that while one set of flip-flops is being reset, another set is already pre-loaded with the next count value. The parallel data loading operates continuously in the background, and the multiple reset circuits ensure that reset operations complete as quickly as possible, minimizing interruptions to the counting sequence and reducing time loss.
Solution Approach 2:
The patent applies preliminary action by pre-loading the next count value into the parallel data input paths before the current count reaches its limit. This allows the counter to be ready for the next value immediately after reset, eliminating the need to wait for sequential loading and reducing the time penalty associated with reset operations.
3Speed
If multiple reset circuits are added to reduce reset delays, then operation speed increases, but device complexity increases
Solution Approach 1:
The patent segments the counter into groups of flip-flops, with each group having its own dedicated reset circuit. This segmentation allows reset operations to be performed in parallel across different groups, improving speed. The modular structure of segmented reset circuits also makes the overall design more manageable and potentially more efficient than a single complex reset circuit.
Data Source
AI summary
A programmable clock divider having reset circuits configured to receive a DP count comprises a first flip-flop having a clock input, a first output, and one of the DP inputs configured to receive a clock signal, a plurality of flip-flops connected to form a ripple counter configured to each receive a DP input, a clock input, and a reset input to provide a first output coupled to the clock input of a subsequent flip-flop of the plurality of flip-flops, each subsequent flip-flop having its clock input coupled to the first output of the preceding flip-flop, a first reset circuit coupled to the flip-flops configured to provide an out signal in response to the flip-flops obtaining the DP count, and a second reset circuit configured to provide a reset signal to the reset input of the plurality of flip-flops in response to the out signal from the first reset circuit.