Clock Divider Reset Sequencing for In-Phase Divided Clock Domains
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Solution Overview
Problem
Ensuring synchronicity of clock signals across different portions of an integrated circuit (IC) during reset is complex, particularly when lower speed clock dividers may stop functioning, leading to incorrect operation or no clock signal, thereby increasing design, test, and manufacturing costs.
Innovation Solution
The implementation of a reset mechanism where a logic block's clock divider completes reset before its local circuitry, ensuring that a divided clock signal is resumed correctly, and using an asynchronous reset to synchronize clock dividers across the IC, ensuring they are in phase with each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock divider is used to provide lower speed clock to part of the logic block, then the logic block can operate at different clock frequencies, but during reset the clock divider may stop functioning causing the logic block to receive incorrect or no clock signal
Solution Approach 1:
The reset signal is applied to the clock divider before the logic block, ensuring the clock divider is already in a known good state before the logic block begins resetting. This preliminary action prevents the clock divider from malfunctioning during the reset process, maintaining reliable clock signal provision throughout the reset sequence.
2Productivity
If lower speed divided clock signals are used for part of the IC, then different portions can operate at different frequencies, but there is an increase in design, test, and manufacturing costs to ensure synchronicity
Solution Approach 1:
The reset control logic for multiple clock dividers is merged into a unified mechanism that manages all clock dividers simultaneously. By combining the reset control functions and using a centralized approach to manage synchronicity across geographically distant clock dividers, the design complexity is reduced while maintaining the ability to operate different IC portions at different frequencies.
3Weight of moving object
If clock dividers are located in geographically distant areas of the IC, then more portions can operate independently, but they must be in phase with each other which requires asynchronous reset mechanisms
Solution Approach 1:
The reset signal is propagated to geographically distant clock dividers in a controlled sequence, with each clock divider receiving the reset signal before it needs to be synchronized. This preliminary resetting action ensures that all distant clock dividers start from a known state before resuming operation, eliminating phase synchronization issues without requiring complex asynchronous reset mechanisms.
Data Source
AI summary
A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.