Clock Divider Resynchronization Circuit for PCIe Gen4 Soft Errors
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Solution Overview
Problem
In fourth-generation PCIe Gen4, frequency division circuits may lose synchronization due to soft errors, leading to unreliable parallel data transmission that fails to meet PCIe standards.
Innovation Solution
A semiconductor circuit with frequency division circuits, phase comparators, and reset signal generators that detect phase shifts and temporarily reset to re-synchronize frequency division clock signals with synchronization reference clocks, ensuring continuous data transmission reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency division circuits are used to enable parallel data transmission in PCIe Gen4, then transmission speed increases, but synchronization reliability deteriorates due to soft errors
Solution Approach 1:
The patent implements a phase comparator that continuously monitors the synchronization state between the reference clock signal and the frequency division clock signal. When a phase shift indicating loss of synchronization is detected, the comparator generates a reset signal to trigger resynchronization. This closed-loop feedback mechanism ensures that synchronization reliability is maintained even as transmission speed increases through frequency division
Solution Approach 2:
The patent employs a reset signal generator that proactively initiates resynchronization before complete desynchronization occurs. By detecting phase shifts early and triggering reset signals in advance, the system prevents synchronization loss from propagating through the parallel data transmission system, thereby maintaining reliability at high transmission speeds
2Speed
If finer process is used to increase transmission speed, then transmission speed increases, but susceptibility to soft errors increases
Solution Approach 1:
The phase comparator continuously monitors clock signal synchronization and provides feedback when phase shifts occur. This real-time detection and correction mechanism compensates for the increased soft error susceptibility of finer process circuits by quickly identifying and correcting errors that occur during high-speed operation
Solution Approach 2:
The system performs self-diagnosis and self-correction through the phase comparator and reset signal generator. When soft errors cause phase shifts in the frequency division circuits, the system automatically detects these errors and triggers resynchronization without external intervention, enabling finer process circuits to operate reliably at higher speeds
Data Source
AI summary
A semiconductor circuit includes a plurality of transmitting circuits, each of which receives a corresponding one of synchronized first clock signals input thereto and includes a first circuit outputting a third clock signal which is generated by dividing the frequency of an unsynchronized second clock signal and is synchronized with the first clock signal, a phase comparator comparing phases of the first clock signal and the third clock signal, and a reset signal generator setting, if a phase shift is detected by the phase comparator, the first signal at a first logic level for a predetermined period. The first circuit enters a reset state during a period in which the first signal is at the first logic level, and, when the first signal changes from the first logic level to a second logic level, is released from a reset state and generates the third clock signal synchronized with the first clock signal.