Clock Divider Switching for Stable Variable-Frequency SoC Clocks
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Solution Overview
Problem
In electronic devices and systems, managing the tradeoff between performance and power consumption is challenging, especially in devices with limited battery storage, as reducing clock signal frequencies can cause jitter and disrupt signal timing, making it difficult to achieve power savings without affecting clock signal stability.
Innovation Solution
A system on a chip (SoC) with multiple clock dividers and a capture circuit that dynamically switches between two or more clock frequencies and associated voltages based on processing bandwidth demands, ensuring stable clock signals without requiring synchronous operation between the system clock and other clock trees.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If clock signal frequency is reduced to save power, then power consumption decreases, but clock signal stability deteriorates causing jitter and timing disruption
Solution Approach 1:
The system dynamically switches between two clock sources with different frequencies based on operational needs. A first clock source operates at a higher frequency for performance-critical operations, while a second clock source operates at a lower frequency for power-saving modes. The system can transition between these sources without disrupting clock signal stability, as each source is independently controlled and switched using synchronized timing mechanisms.
Solution Approach 2:
The invention changes the frequency parameter of the clock signal by selecting between multiple clock sources with different predetermined frequencies. The controller monitors system state and adjusts the clock frequency parameter dynamically, switching between the first clock source (higher frequency) and the second clock source (lower frequency) to optimize the tradeoff between power consumption and performance while maintaining signal stability through controlled transitions.
2Adaptability or versatility
If system clock frequency is changed while application is running, then power management flexibility improves, but system complexity and operational disruption increase
Solution Approach 1:
The system prepares for clock frequency changes by having multiple clock sources pre-configured and ready. Before switching frequencies, the controller ensures the second clock source is already operating and synchronized. This preliminary preparation allows for seamless transitions without requiring complex real-time adjustments or disrupting running applications, thereby reducing operational complexity despite having multiple clock sources.
Solution Approach 2:
The controller acts as an intermediary between the multiple clock sources and the system components. It manages the switching between clock sources, handles synchronization, and ensures smooth transitions without disrupting application execution. This intermediary role simplifies the overall system architecture by centralizing the complexity of clock management in a dedicated component rather than distributing it throughout the system.
Data Source
AI summary
In some aspects, the techniques described herein relate to a system on a chip (SoC) including a first clock divider configured to: receive an oscillator signal at a first frequency; produce, based on the oscillator signal: a first clock signal at the first frequency; and a second clock signal at a second frequency, the second frequency being a division of the first frequency. The first clock divider can selectively provide the first clock signal or the second clock signal as a first output clock signal based on a scaling configuration signal. The first clock divider can produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal. The SoC can include a second clock divider configured to provide a second clock output signal based on the first output clock signal and the frequency indication signal.