Clock Divider Synchronization for Variable-Core Automotive Clocks
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Solution Overview
Problem
Existing clock signal generation systems in automotive electronic systems face challenges in reducing power consumption while maintaining synchronization of clock signals across varying frequencies, often requiring additional synchronizer logic and increasing complexity.
Innovation Solution
A clock signal generation system that includes a clock signal generating circuit with a divider circuit and a controller module, allowing for a selectable first clock rate while maintaining a constant second clock rate for peripheral devices, using a fractional divider to synchronize clock signals and reduce power consumption without the need for additional synchronizer logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock rate applied to the microcontroller core is reduced to reduce power consumption, then power consumption is reduced, but the clock rate of clock signals applied to peripheral components must also change, requiring additional clock generating circuits and synchronizer logic
Solution Approach 1:
The system segments the clock signal distribution into two independent paths: a first clock signal path for the microcontroller core with variable frequency, and a second clock signal path for peripheral components with constant frequency. This segmentation allows each path to be optimized independently, enabling power reduction in the core while maintaining stable operation of peripherals without requiring complex synchronizer logic across the entire system.
Solution Approach 2:
The invention applies different clock frequency characteristics to different parts of the system: the microcontroller core receives a variable frequency clock signal optimized for power consumption, while peripheral components receive a constant frequency clock signal optimized for stable operation. This local differentiation allows each component to operate under its optimal conditions without imposing complexity on the entire system.
2Stability of the object's composition
If additional clock generating circuits are provided to maintain constant clock rate for peripheral components, then constant clock rate is maintained for peripherals, but device complexity increases
Solution Approach 1:
The system employs dynamic frequency selection through a first clock signal generating circuit that can operate at multiple frequency levels. Instead of using static additional clock generating circuits for each peripheral, the invention dynamically adjusts the first clock signal frequency based on system requirements, while a simple divider circuit derives the constant second clock signal. This dynamic approach replaces complex static circuitry with a more efficient frequency multiplication and division scheme.
Solution Approach 2:
The first clock signal generating circuit serves multiple functions: it directly clocks the microcontroller core and simultaneously serves as the input to the divider circuit that generates the second clock signal for peripherals. This multi-functionality eliminates the need for separate dedicated clock generating circuits for each peripheral component, reducing overall system complexity while maintaining constant clock rates where needed.
Data Source
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AI summary
A clock signal generation system (10) comprises a clock signal generating circuit (12) arranged to provide a first clock signal having a selectable first clock rate; a divider circuit (14) connected to receive the first clock signal and arranged to generate, depending on a division factor, a second clock signal from the first clock signal, having a constant second clock rate and being synchronized with the first clock signal; and a controller module (16) connected to the divider circuit and arranged to change the division factor when a different first clock rate is selected, to keep the second clock rate constant and the second clock signal synchronized with the first clock signal.