Clock Divider Monitoring for Input Clock Tamper Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data processing systems face challenges in detecting tampering with clock signals, such as frequency alterations or pulse glitches, without significantly increasing area, cost, or power consumption.
Innovation Solution
An apparatus and method utilizing multiple clock divider circuits that generate monitored clock signals by dividing the input clock signal, each using a different leading edge, with analysis and alarm generation circuitry to detect variations in clock signal width over multiple cycles, enabling efficient detection of tampering attempts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock divider circuits are used to detect clock signal irregularities, then detection reliability is improved, but device complexity and area increase
Solution Approach 1:
The system divides the clock signal monitoring function into multiple independent clock divider circuits, each processing a different clock cycle. This segmentation allows parallel detection of clock irregularities across multiple cycles, improving reliability through redundancy while keeping each individual divider circuit simple and manageable in size.
Solution Approach 2:
The invention transitions from single-cycle clock monitoring to multi-cycle monitoring by introducing a temporal dimension. Each clock divider circuit processes a different clock cycle, and the analysis circuitry compares width indications across multiple cycles, adding time as an additional dimension for detecting clock signal irregularities.
2Reliability
If multiple clock divider circuits are used to detect clock signal irregularities, then detection reliability is improved, but power consumption increases
Solution Approach 1:
The monitoring function is segmented across multiple clock cycles rather than requiring all circuits to operate simultaneously at full power. Each clock divider circuit processes individual clock cycles, allowing for more efficient power management while maintaining detection reliability through multi-cycle analysis.
Solution Approach 2:
Instead of using a single complex high-power monitoring circuit, the system uses multiple simpler, lower-power clock divider circuits that process different clock cycles. The collective output of these simpler circuits achieves the same detection reliability as a single complex circuit would provide.
3Measurement precision
If clock signal width is monitored over multiple cycles, then detection precision for small variations is improved, but measurement time increases
Solution Approach 1:
The system uses periodic sampling of clock cycle widths across multiple cycles to detect irregularities. By analyzing the periodical pattern of clock cycles and comparing width indications systematically, the system achieves high detection precision while minimizing the time required, as it doesn't need to monitor indefinitely but rather through a defined multi-cycle period.
Solution Approach 2:
The analysis circuitry continuously compares width indications from multiple clock cycles and provides feedback to determine when an irregularity is detected. This feedback mechanism allows the system to achieve high precision detection efficiently by stopping analysis once sufficient evidence of an irregularity or normal operation is gathered across the monitored cycles.
Data Source
AI summary
An apparatus has an input interface for receiving an input clock signal, and a plurality N of clock divider circuits, each clock divider circuit generating a corresponding monitored clock signal by dividing the input clock signal by N. Each clock divider circuit is arranged, when generating a leading edge of each clock cycle of its corresponding monitored clock signal, to use a leading edge of a different clock cycle of the input clock signal to the clock cycle of the input clock signal used by any other of the clock divider circuits. Analysis circuitry provided in association with each clock divider circuit produces a width indication for each clock cycle of the corresponding monitored clock signal. Alarm generation circuitry then triggers an alarm signal when, for any of the monitored clock signals, a variation in the width indication is detected over multiple clock cycles of that monitored clock signal.