Clock Divider Voltage Swing Control for Duty Cycle Distortion
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Solution Overview
Problem
Conventional duty cycle correction circuits for semiconductor memories are large and consume excessive power, making them undesirable for reducing duty cycle distortion in clock signals, which can lead to erroneous operations.
Innovation Solution
A semiconductor device with a receiver circuit and clock divider circuit that generates internal clocks with reduced duty cycle distortion by adjusting the voltage swing and phase relationships of clock signals, using a control signal to modify the characteristics of output clocks and providing multiphase clocks with lower frequency and reduced duty cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional duty cycle correction circuits are used, then duty cycle distortion is corrected, but the circuit area and power consumption increase
Solution Approach 1:
The patent changes the voltage swing parameter of the clock signal to correct duty cycle distortion. By adjusting the voltage swing of the input clock signal, the circuit achieves duty cycle correction without requiring a large conventional correction circuit, thus reducing the circuit area while maintaining reliability.
2Reliability
If conventional duty cycle correction circuits are used, then duty cycle distortion is corrected, but power consumption increases
Solution Approach 1:
The patent modifies the voltage swing parameter of the clock signal to achieve duty cycle correction. This parameter-based approach corrects duty cycle distortion while consuming less power compared to conventional correction circuits that require additional active components and higher power consumption.
3Measurement precision
If voltage swing is adjusted to reduce duty cycle distortion, then timing accuracy improves, but clock signal characteristics change
Solution Approach 1:
The patent dynamically adjusts the voltage swing of the clock signal based on the specific duty cycle distortion conditions. This dynamic adjustment allows the circuit to maintain timing accuracy while adapting to different clock signal requirements, ensuring compatibility across various applications through flexible parameter modulation.
Data Source
AI summary
Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.