Clock Dividing Frequency Circuit for Power Management ICs
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Solution Overview
Problem
Existing clock dividing frequency circuits face challenges in smoothly and proportionally adjusting the clock frequency according to voltage differences, leading to increased output voltage ripple and deteriorated load regulation at light load states in power management integrated circuits.
Innovation Solution
A clock dividing frequency circuit comprising a controlled current source, a ramp signal generating circuit, and a dividing frequency pulse generating circuit, where the frequency of the pulse-width modulation signal varies with the compensation signal, allowing the operating frequency of the power stage circuit to decrease and synchronize with the system clock, reducing output voltage ripple and improving load regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the system clock frequency is digitally divided, then the clock frequency can be reduced, but it becomes difficult to change the clock frequency smoothly and proportionally according to the voltage difference
Solution Approach 1:
The patent changes the control parameter from digital division ratios to analog voltage differences. The voltage difference between two nodes is converted into a proportional clock frequency adjustment, enabling smooth and continuous frequency changes rather than discrete digital steps. This resolves the contradiction by making frequency adjustment as easy as changing voltage levels.
2Reliability
If the local clock frequency is reduced to protect the power stage circuit, then circuit protection is improved, but output voltage ripple increases and load regulation deteriorates at light load states
Solution Approach 1:
The patent implements dynamic clock frequency adjustment based on operating conditions. At light load states, the clock frequency is automatically reduced to minimize output voltage ripple and improve load regulation. At full load states, the frequency increases to maintain circuit protection and stable operation. This dynamic adaptation resolves the contradiction by optimizing frequency for each operating condition.
3Area of stationary object
If all channels share the same system clock, then chip space is saved and noise performance is optimized, but each channel cannot independently adjust its clock frequency according to its specific requirements
Solution Approach 1:
The patent segments the clock frequency control for each channel while maintaining a shared system clock source. Each channel receives the same system clock but can independently adjust its local clock frequency based on its specific requirements. This segmentation allows both space efficiency (shared clock source) and adaptability (independent frequency control).
Data Source
AI summary
A clock dividing frequency circuit can include: a controlled current source configured to generate a driving current that varies with a dividing frequency control signal; a ramp signal generating circuit configured to generate a ramp signal having a slope that varies according to the driving current, where the ramp signal is reset according to pulses of a dividing frequency clock signal; and a dividing frequency pulse generating circuit configured to generate the dividing frequency clock signal by a dividing frequency operation according to the ramp signal and a system clock signal.