Clock Division Counting Circuit for High-Frequency Latency Control
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Solution Overview
Problem
As the frequency of clock signals in synchronous integrated circuits increases, the margin for correct operation decreases, leading to noise and incorrect counting of clock signals during path delay values, affecting latency control circuits.
Innovation Solution
A counting circuit with a clock division unit that divides the reference clock signal and generates a divided clock signal, along with a counting unit that counts the divided clock signal, and a counting control unit that enables counting during a specific period, increasing the margin for accurate clock counting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of clock signals is increased to improve operation speed, then productivity is improved, but measurement precision of clock counting deteriorates due to reduced margin for correct operation
Solution Approach 1:
The patent divides the high-frequency clock signal into multiple lower-frequency signals using delay units and selection units. By segmenting the counting process across multiple divided clock signals, the system maintains accurate counting capability while supporting higher overall operation speeds. The delay units create time-separated versions of the clock signal, allowing the counter to process each divided signal with sufficient margin.
Solution Approach 2:
The patent applies preliminary delay to the clock signal to create divided clock signals before counting. By pre-processing the clock signal through delay units and selection units, the system prepares multiple timing versions that enable accurate counting even at high frequencies. This preliminary action of dividing the clock signal ensures that each counting operation has adequate time margin.
2Productivity
If the frequency of clock signals is increased, then productivity is improved, but reliability deteriorates due to noise and incorrect counting
Solution Approach 1:
The patent segments the high-frequency clock signal into multiple lower-frequency divided clock signals through delay units and selection units. This segmentation reduces the frequency burden on individual counting operations, thereby improving reliability by minimizing noise and incorrect counting while maintaining high overall productivity through parallel processing of multiple divided signals.
Solution Approach 2:
The patent introduces delay units and selection units as intermediary components between the high-frequency clock signal and the counter. These intermediaries process and condition the clock signal, creating divided versions that are more reliable for counting operations. The selection unit acts as a mediator that chooses appropriate divided clock signals based on timing requirements, ensuring reliable operation.
Data Source
AI summary
A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.