Clock Generation by Sectioned Integer Division for Low Deviation
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Solution Overview
Problem
Conventional clock generating circuits using integer number frequency division methods face challenges in minimizing data rate deviation and temporal fluctuations, leading to increased costs and power consumption, especially when generating clocks with various frequencies for communication systems.
Innovation Solution
A method involving the calculation of two frequency division numbers, N1 and N2, where N2 is derived from N1, allowing for frequency division within specific sections of the oversampling counter value, enabling the generation of clocks with reduced data rate deviation and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If integer number frequency division method is used, then device complexity is reduced, but data rate deviation increases
Solution Approach 1:
The patent segments the frequency division process into multiple stages: first dividing the master clock frequency by an integer N to obtain an intermediate frequency, then dividing by another integer M to achieve the final data rate clock. This multi-stage segmentation allows better control over the division ratio while maintaining integer division simplicity, thereby reducing data rate deviation without significantly increasing circuit complexity.
Solution Approach 2:
The patent changes the division parameters by introducing two separate integer divisors (N and M) instead of a single divisor. By optimizing the combination of N and M, the system achieves a division ratio that more closely matches the required data rate, minimizing deviation while keeping the circuit structure relatively simple.
2Use of energy by moving object
If conventional frequency division method is used, then power consumption is reduced, but temporal fluctuation increases
Solution Approach 1:
The patent divides the frequency division into multiple integer stages (N and M), which allows for more precise control over the division ratio. This segmentation enables the system to achieve the target frequency with smaller temporal fluctuations while maintaining a power-efficient integer division approach, avoiding the need for more complex and power-hungry fractional division circuits.
Solution Approach 2:
The patent incorporates a feedback mechanism where the divided clock signals are monitored and the division ratios (N and M) can be adjusted to minimize temporal fluctuations. This feedback control allows the system to maintain stability and reduce jitter while continuing to use power-efficient integer division methods.
3Manufacturing precision
If data rate deviation is minimized, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent achieves precise data rate control by segmenting the frequency division into multiple integer stages with divisors N and M. This segmentation provides fine-grained control over the final frequency while using only simple integer division circuits, avoiding the need for complex fractional division hardware and thereby maintaining manufacturing precision without excessive complexity increase.
Solution Approach 2:
The patent designs a universal clock generating circuit that can accommodate different data rates by simply changing the integer divisors N and M. This multi-functional design allows the same circuit structure to achieve precise frequency control for various applications without requiring custom complex circuits for each specific data rate, thus improving manufacturing precision while controlling complexity.
Data Source
AI summary
A method of generating a clock includes the steps of calculating a first frequency division number through dividing a frequency of an input clock by a target frequency and a specific integer k (k≧2); calculating a second frequency division number according to the first frequency division number; dividing a period of time of one cycle of the target frequency by the specific integer k to obtain sections in a number of the specific integer k; dividing the frequency of the input clock with the second frequency division number within one of the sections; dividing the frequency of the input clock with the second frequency division number within each remaining one of the sections in a number of (k−1); and generating the clock having a frequency with one cycle equal to a period of time corresponding to each of the sections.